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review.coreboot.org / coreboot / fcf776fd02d60ab01b885ce48beae929098d6aad / . / Documentation / Intel / Board / board.html
blob: 47d329515dd2f25503cfd83e8eeeb7d238b5ff97 [file] [log] [blame]
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]1<!DOCTYPE html>
2<html>
3 <head>
4 <title>Board</title>
5 </head>
6 <body>
7
8<h1>x86 Board Development</h1>
9<p>
10 Board development requires System-on-a-Chip (SoC) support.
11 The combined steps are listed
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]12 <a target="_blank" href="../development.html">here</a>.
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]13 The development steps for the board are listed below:
14</p>
15<ol>
16 <li><a href="#RequiredFiles">Required Files</a></li>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]17 <li>Enable <a href="#SerialOutput">Serial Output</a></li>
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame^]18 <li>Load the <a href="#SpdData">Memory Timing Data</a></li>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]19</ol>
20
21
22<hr>
23<h1><a name="RequiredFiles">Required Files</a></h1>
24<p>
25 Create the board directory as src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;.
26</p>
27
28<p>
29 The following files are required to build a new board:
30</p>
31<ol>
32 <li>Kconfig.name - Defines the Kconfig value for the board</li>
33 <li>Kconfig
34 <ol type="A">
35 <li>Selects the SoC for the board and specifies the SPI flash size
36 <ol type="I">
37 <li>BOARD_ROMSIZE_KB_&lt;Size&gt;</li>
38 <li>SOC_&lt;Vendor&gt;_&lt;Chip Family&gt;</li>
39 </ol>
40 </li>
41 <li>Declare the Kconfig values for:
42 <ol type="I">
43 <li>MAINBOARD_DIR</li>
44 <li>MAINBOARD_PART_NUMBER</li>
45 <li>MAINBOARD_VENDOR</li>
46 </ol>
47 </li>
48 </ol>
49 </li>
50 <li>devicetree.cb - Enable root bridge and serial port
51 <ol type="A">
52 <li>The first line must be "chip soc/Intel/&lt;soc family&gt;";
53 this path is used by the generated static.c to include the chip.h
54 header file
55 </li>
56 </ol>
57 </li>
58 <li>romstage.c
59 <ol type="A">
60 <li>Add routine mainboard_romstage_entry which calls romstage_common</li>
61 </ol>
62 </li>
63 <li>Configure coreboot build:
64 <ol type="A">
65 <li>Set LOCALVERSION</li>
66 <li>FLASHMAP_OFFSET = 0x00700000</li>
67 <li>Select vendor for the board</li>
68 <li>Select the board</li>
69 <li>CBFS_SIZE = 0x00100000</li>
70 <li>Set the CPU_MICROCODE_CBFS_LEN</li>
71 <li>Set the CPU_MICROCODE_CBFS_LOC</li>
72 <li>Set the FSP_IMAGE_ID_STRING</li>
73 <li>Set the FSP_LOC</li>
74 <li>Disable GOP_SUPPORT</li>
75 <li>No payload</li>
76 <li>Choose the default value for all other options</li>
77 </ol>
78 </li>
79</ol>
80
81
82<hr>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]83<h1><a name="SerialOutput">Enable Serial Output</a></h1>
84<p>
85 Use the following steps to enable serial output:
86</p>
87<ol>
88 <li>Implement the car_mainboard_pre_console_init routine in the com_init.c
89 file:
90 <ol type="A">
91 <li>Power on and enable the UART controller</li>
92 <li>Connect the UART receive and transmit data lines to the
93 appropriate SoC pins
94 </li>
95 </ol>
96 </li>
97 <li>Add Makefile.inc
98 <ol type="A">
99 <li>Add com_init.c to romstage</li>
100 </ol>
101 </li>
102</ol>
103
104
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame^]105<hr>
106<h1><a name="SpdData">Memory Timing Data</a></h1>
107<p>
108 Memory timing data is located in the flash. This data is in the format of
109 <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
110 (SPD) data.
111 Use the following steps to load the SPD data:
112</p>
113<ol>
114 <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
115 display of the SPD data being passed to MemoryInit
116 </li>
117 <li>Create an "spd" subdirectory</li>
118 <li>Create an spd/spd.c file for the SPD implementation
119 <ol type="A">
120 <li>Implement the mainboard_fill_spd_data routine
121 <ol type="i">
122 <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
123 <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
124 <li>Set the DIMM channel configuration</li>
125 </ol>
126 </li>
127 </ol>
128 </li>
129 <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
130 <li>Create spd/Makefile.inc
131 <ol type="A">
132 <li>Add spd.c to romstage</li>
133 <li>Add the .spd.hex file to SPD_SOURCES</li>
134 </ol>
135 </li>
136 <li>Edit Makefile.inc to add the spd subdirectory</li>
137 <li>Edit romstage.c
138 <ol type="A">
139 <li>Call mainboard_fill_spd_data</li>
140 <li>Add mainboard_memory_init_params to copy the SPD and DRAM
141 configuration data from the pei_data structure into the UPDs
142 for MemoryInit
143 </li>
144 </ol>
145 </li>
146 <li>Edit devicetree.cb
147 <ol type="A">
148 <li>Include the UPD parameters for MemoryInit except for:
149 <ul>
150 <li>Address of SPD data</li>
151 <li>DRAM configuration set above</li>
152 </ul>
153 </li>
154 </ol>
155 </li>
156 <li>A working FSP
157 <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
158 routine is required to complete debugging</li>
159 <li>Debug the result until port 0x80 outputs
160 <ol type="A">
161 <li>0x34:
162 - Just after entering
163 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
164 </li>
165 <li>0x36:
166 - Just before displaying the
167 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
168 for FSP MemoryInit
169 </li>
170 <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
171 - Just before calling FSP
172 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
173 </li>
174 <li>0x37:
175 - Just after returning from FSP
176 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
177 </li>
178 </ol>
179 </li>
180 <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
181</ol>
182
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]183
184<hr>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]185<p>Modified: 31 January 2016</p>
186 </body>
187</html>