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review.coreboot.org / coreboot / de8c7e39bce97f13e09e53a3a1bdf4edcfebec79 / . / Documentation / Intel / Board / board.html
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Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]1<!DOCTYPE html>
2<html>
3 <head>
4 <title>Board</title>
5 </head>
6 <body>
7
8<h1>x86 Board Development</h1>
9<p>
10 Board development requires System-on-a-Chip (SoC) support.
11 The combined steps are listed
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]12 <a target="_blank" href="../development.html">here</a>.
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]13 The development steps for the board are listed below:
14</p>
15<ol>
16 <li><a href="#RequiredFiles">Required Files</a></li>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]17 <li>Enable <a href="#SerialOutput">Serial Output</a></li>
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame]18 <li>Load the <a href="#SpdData">Memory Timing Data</a></li>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame^]19 <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]20</ol>
21
22
23<hr>
24<h1><a name="RequiredFiles">Required Files</a></h1>
25<p>
26 Create the board directory as src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;.
27</p>
28
29<p>
30 The following files are required to build a new board:
31</p>
32<ol>
33 <li>Kconfig.name - Defines the Kconfig value for the board</li>
34 <li>Kconfig
35 <ol type="A">
36 <li>Selects the SoC for the board and specifies the SPI flash size
37 <ol type="I">
38 <li>BOARD_ROMSIZE_KB_&lt;Size&gt;</li>
39 <li>SOC_&lt;Vendor&gt;_&lt;Chip Family&gt;</li>
40 </ol>
41 </li>
42 <li>Declare the Kconfig values for:
43 <ol type="I">
44 <li>MAINBOARD_DIR</li>
45 <li>MAINBOARD_PART_NUMBER</li>
46 <li>MAINBOARD_VENDOR</li>
47 </ol>
48 </li>
49 </ol>
50 </li>
51 <li>devicetree.cb - Enable root bridge and serial port
52 <ol type="A">
53 <li>The first line must be "chip soc/Intel/&lt;soc family&gt;";
54 this path is used by the generated static.c to include the chip.h
55 header file
56 </li>
57 </ol>
58 </li>
59 <li>romstage.c
60 <ol type="A">
61 <li>Add routine mainboard_romstage_entry which calls romstage_common</li>
62 </ol>
63 </li>
64 <li>Configure coreboot build:
65 <ol type="A">
66 <li>Set LOCALVERSION</li>
67 <li>FLASHMAP_OFFSET = 0x00700000</li>
68 <li>Select vendor for the board</li>
69 <li>Select the board</li>
70 <li>CBFS_SIZE = 0x00100000</li>
71 <li>Set the CPU_MICROCODE_CBFS_LEN</li>
72 <li>Set the CPU_MICROCODE_CBFS_LOC</li>
73 <li>Set the FSP_IMAGE_ID_STRING</li>
74 <li>Set the FSP_LOC</li>
75 <li>Disable GOP_SUPPORT</li>
76 <li>No payload</li>
77 <li>Choose the default value for all other options</li>
78 </ol>
79 </li>
80</ol>
81
82
83<hr>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]84<h1><a name="SerialOutput">Enable Serial Output</a></h1>
85<p>
86 Use the following steps to enable serial output:
87</p>
88<ol>
89 <li>Implement the car_mainboard_pre_console_init routine in the com_init.c
90 file:
91 <ol type="A">
92 <li>Power on and enable the UART controller</li>
93 <li>Connect the UART receive and transmit data lines to the
94 appropriate SoC pins
95 </li>
96 </ol>
97 </li>
98 <li>Add Makefile.inc
99 <ol type="A">
100 <li>Add com_init.c to romstage</li>
101 </ol>
102 </li>
103</ol>
104
105
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame]106<hr>
107<h1><a name="SpdData">Memory Timing Data</a></h1>
108<p>
109 Memory timing data is located in the flash. This data is in the format of
110 <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
111 (SPD) data.
112 Use the following steps to load the SPD data:
113</p>
114<ol>
115 <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
116 display of the SPD data being passed to MemoryInit
117 </li>
118 <li>Create an "spd" subdirectory</li>
119 <li>Create an spd/spd.c file for the SPD implementation
120 <ol type="A">
121 <li>Implement the mainboard_fill_spd_data routine
122 <ol type="i">
123 <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
124 <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
125 <li>Set the DIMM channel configuration</li>
126 </ol>
127 </li>
128 </ol>
129 </li>
130 <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
131 <li>Create spd/Makefile.inc
132 <ol type="A">
133 <li>Add spd.c to romstage</li>
134 <li>Add the .spd.hex file to SPD_SOURCES</li>
135 </ol>
136 </li>
137 <li>Edit Makefile.inc to add the spd subdirectory</li>
138 <li>Edit romstage.c
139 <ol type="A">
140 <li>Call mainboard_fill_spd_data</li>
141 <li>Add mainboard_memory_init_params to copy the SPD and DRAM
142 configuration data from the pei_data structure into the UPDs
143 for MemoryInit
144 </li>
145 </ol>
146 </li>
147 <li>Edit devicetree.cb
148 <ol type="A">
149 <li>Include the UPD parameters for MemoryInit except for:
150 <ul>
151 <li>Address of SPD data</li>
152 <li>DRAM configuration set above</li>
153 </ul>
154 </li>
155 </ol>
156 </li>
157 <li>A working FSP
158 <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
159 routine is required to complete debugging</li>
160 <li>Debug the result until port 0x80 outputs
161 <ol type="A">
162 <li>0x34:
163 - Just after entering
164 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
165 </li>
166 <li>0x36:
167 - Just before displaying the
168 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
169 for FSP MemoryInit
170 </li>
171 <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
172 - Just before calling FSP
173 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
174 </li>
175 <li>0x37:
176 - Just after returning from FSP
177 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
178 </li>
179 </ol>
180 </li>
181 <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
182</ol>
183
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]184
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame^]185
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]186<hr>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame^]187<h1><a name="DisablePciDevices">Disable PCI Devices</a></h1>
188<p>
189 Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
190 of the devices in the system. Edit the devicetree.cb file:
191</p>
192<ol>
193 <li>Edit the devicetree.cb file:
194 <ol type="A">
195 <li>Add an entry for a PCI device.function and turn it off. The entry
196 should look similar to:
197<pre><code>device pci 14.0 off end</code></pre>
198 </li>
199 <li>Turn on the devices for:
200 <ul>
201 <li>Memory Controller</li>
202 <li>Debug serial device</li>
203 </ul>
204 </li>
205 </ol>
206 </li>
207 <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
208</ol>
209
210
211<hr>
212<p>Modified: 15 February 2016</p>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]213 </body>
214</html>