Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 3 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 4 | #include <assert.h> |
| 5 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 7 | #include <delay.h> |
| 8 | #include <soc/addressmap.h> |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 9 | #include <soc/clock.h> |
Lin Huang | f5702e7 | 2016-03-19 22:45:19 +0800 | [diff] [blame] | 10 | #include <soc/grf.h> |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 11 | #include <soc/i2c.h> |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 12 | #include <soc/soc.h> |
| 13 | #include <stdint.h> |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 14 | #include <string.h> |
| 15 | |
| 16 | struct pll_div { |
| 17 | u32 refdiv; |
| 18 | u32 fbdiv; |
| 19 | u32 postdiv1; |
| 20 | u32 postdiv2; |
| 21 | u32 frac; |
Lin Huang | e3d78b8 | 2016-06-28 11:10:54 +0800 | [diff] [blame] | 22 | u32 freq; |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 23 | }; |
| 24 | |
| 25 | #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ |
| 26 | .refdiv = _refdiv,\ |
| 27 | .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ |
Lin Huang | e3d78b8 | 2016-06-28 11:10:54 +0800 | [diff] [blame] | 28 | .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};\ |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 29 | _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ |
| 30 | OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 31 | STRINGIFY(hz) " Hz cannot be hit with PLL "\ |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 32 | "divisors on line " STRINGIFY(__LINE__)) |
| 33 | |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 34 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); |
| 35 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 3, 1); |
| 36 | static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 3, 2, 1); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 37 | |
Eric Gao | 61e6c44 | 2016-07-29 12:34:32 +0800 | [diff] [blame] | 38 | static const struct pll_div apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1); |
| 39 | static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 40 | |
Lin Huang | 3d703bc | 2016-06-28 14:19:18 +0800 | [diff] [blame] | 41 | static const struct pll_div *apll_cfgs[] = { |
Eric Gao | 61e6c44 | 2016-07-29 12:34:32 +0800 | [diff] [blame] | 42 | [APLL_1512_MHZ] = &apll_1512_cfg, |
Lin Huang | 3d703bc | 2016-06-28 14:19:18 +0800 | [diff] [blame] | 43 | [APLL_600_MHZ] = &apll_600_cfg, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 44 | }; |
| 45 | |
| 46 | enum { |
| 47 | /* PLL_CON0 */ |
| 48 | PLL_FBDIV_MASK = 0xfff, |
| 49 | PLL_FBDIV_SHIFT = 0, |
| 50 | |
| 51 | /* PLL_CON1 */ |
| 52 | PLL_POSTDIV2_MASK = 0x7, |
| 53 | PLL_POSTDIV2_SHIFT = 12, |
| 54 | PLL_POSTDIV1_MASK = 0x7, |
| 55 | PLL_POSTDIV1_SHIFT = 8, |
| 56 | PLL_REFDIV_MASK = 0x3f, |
| 57 | PLL_REFDIV_SHIFT = 0, |
| 58 | |
| 59 | /* PLL_CON2 */ |
| 60 | PLL_LOCK_STATUS_MASK = 1, |
| 61 | PLL_LOCK_STATUS_SHIFT = 31, |
| 62 | PLL_FRACDIV_MASK = 0xffffff, |
| 63 | PLL_FRACDIV_SHIFT = 0, |
| 64 | |
| 65 | /* PLL_CON3 */ |
| 66 | PLL_MODE_MASK = 3, |
| 67 | PLL_MODE_SHIFT = 8, |
| 68 | PLL_MODE_SLOW = 0, |
| 69 | PLL_MODE_NORM, |
| 70 | PLL_MODE_DEEP, |
| 71 | PLL_DSMPD_MASK = 1, |
| 72 | PLL_DSMPD_SHIFT = 3, |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 73 | PLL_FRAC_MODE = 0, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 74 | PLL_INTEGER_MODE = 1, |
| 75 | |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 76 | /* PLL_CON4 */ |
| 77 | PLL_SSMOD_BP_MASK = 1, |
| 78 | PLL_SSMOD_BP_SHIFT = 0, |
| 79 | PLL_SSMOD_DIS_SSCG_MASK = 1, |
| 80 | PLL_SSMOD_DIS_SSCG_SHIFT = 1, |
| 81 | PLL_SSMOD_RESET_MASK = 1, |
| 82 | PLL_SSMOD_RESET_SHIFT = 2, |
| 83 | PLL_SSMOD_DOWNSPEAD_MASK = 1, |
| 84 | PLL_SSMOD_DOWNSPEAD_SHIFT = 3, |
| 85 | PLL_SSMOD_DIVVAL_MASK = 0Xf, |
| 86 | PLL_SSMOD_DIVVAL_SHIFT = 4, |
| 87 | PLL_SSMOD_SPREADAMP_MASK = 0x1f, |
| 88 | PLL_SSMOD_SPREADAMP_SHIFT = 8, |
| 89 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 90 | /* PMUCRU_CLKSEL_CON0 */ |
| 91 | PMU_PCLK_DIV_CON_MASK = 0x1f, |
| 92 | PMU_PCLK_DIV_CON_SHIFT = 0, |
| 93 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 94 | /* PMUCRU_CLKSEL_CON1 */ |
| 95 | SPI3_PLL_SEL_MASK = 1, |
| 96 | SPI3_PLL_SEL_SHIFT = 7, |
| 97 | SPI3_PLL_SEL_24M = 0, |
| 98 | SPI3_PLL_SEL_PPLL = 1, |
| 99 | SPI3_DIV_CON_MASK = 0x7f, |
| 100 | SPI3_DIV_CON_SHIFT = 0x0, |
| 101 | |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 102 | /* PMUCRU_CLKSEL_CON2 */ |
| 103 | I2C_DIV_CON_MASK = 0x7f, |
| 104 | I2C8_DIV_CON_SHIFT = 8, |
| 105 | I2C0_DIV_CON_SHIFT = 0, |
| 106 | |
| 107 | /* PMUCRU_CLKSEL_CON3 */ |
| 108 | I2C4_DIV_CON_SHIFT = 0, |
| 109 | |
Lin Huang | bdd06de | 2016-06-28 15:21:20 +0800 | [diff] [blame] | 110 | /* CLKSEL_CON0 / CLKSEL_CON2 */ |
| 111 | ACLKM_CORE_DIV_CON_MASK = 0x1f, |
| 112 | ACLKM_CORE_DIV_CON_SHIFT = 8, |
| 113 | CLK_CORE_PLL_SEL_MASK = 3, |
| 114 | CLK_CORE_PLL_SEL_SHIFT = 6, |
| 115 | CLK_CORE_PLL_SEL_ALPLL = 0x0, |
| 116 | CLK_CORE_PLL_SEL_ABPLL = 0x1, |
| 117 | CLK_CORE_PLL_SEL_DPLL = 0x10, |
| 118 | CLK_CORE_PLL_SEL_GPLL = 0x11, |
| 119 | CLK_CORE_DIV_MASK = 0x1f, |
| 120 | CLK_CORE_DIV_SHIFT = 0, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 121 | |
Lin Huang | bdd06de | 2016-06-28 15:21:20 +0800 | [diff] [blame] | 122 | /* CLKSEL_CON1 / CLKSEL_CON3 */ |
| 123 | PCLK_DBG_DIV_MASK = 0x1f, |
| 124 | PCLK_DBG_DIV_SHIFT = 0x8, |
| 125 | ATCLK_CORE_DIV_MASK = 0x1f, |
| 126 | ATCLK_CORE_DIV_SHIFT = 0, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 127 | |
| 128 | /* CLKSEL_CON14 */ |
| 129 | PCLK_PERIHP_DIV_CON_MASK = 0x7, |
| 130 | PCLK_PERIHP_DIV_CON_SHIFT = 12, |
| 131 | HCLK_PERIHP_DIV_CON_MASK = 3, |
| 132 | HCLK_PERIHP_DIV_CON_SHIFT = 8, |
| 133 | ACLK_PERIHP_PLL_SEL_MASK = 1, |
| 134 | ACLK_PERIHP_PLL_SEL_SHIFT = 7, |
| 135 | ACLK_PERIHP_PLL_SEL_CPLL = 0, |
| 136 | ACLK_PERIHP_PLL_SEL_GPLL = 1, |
| 137 | ACLK_PERIHP_DIV_CON_MASK = 0x1f, |
| 138 | ACLK_PERIHP_DIV_CON_SHIFT = 0, |
| 139 | |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 140 | /* CLKSEL_CON21 */ |
| 141 | ACLK_EMMC_PLL_SEL_MASK = 0x1, |
| 142 | ACLK_EMMC_PLL_SEL_SHIFT = 7, |
| 143 | ACLK_EMMC_PLL_SEL_GPLL = 0x1, |
| 144 | ACLK_EMMC_DIV_CON_MASK = 0x1f, |
| 145 | ACLK_EMMC_DIV_CON_SHIFT = 0, |
| 146 | |
| 147 | /* CLKSEL_CON22 */ |
| 148 | CLK_EMMC_PLL_MASK = 0x7, |
| 149 | CLK_EMMC_PLL_SHIFT = 8, |
| 150 | CLK_EMMC_PLL_SEL_GPLL = 0x1, |
| 151 | CLK_EMMC_DIV_CON_MASK = 0x7f, |
| 152 | CLK_EMMC_DIV_CON_SHIFT = 0, |
| 153 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 154 | /* CLKSEL_CON23 */ |
| 155 | PCLK_PERILP0_DIV_CON_MASK = 0x7, |
| 156 | PCLK_PERILP0_DIV_CON_SHIFT = 12, |
| 157 | HCLK_PERILP0_DIV_CON_MASK = 3, |
| 158 | HCLK_PERILP0_DIV_CON_SHIFT = 8, |
| 159 | ACLK_PERILP0_PLL_SEL_MASK = 1, |
| 160 | ACLK_PERILP0_PLL_SEL_SHIFT = 7, |
| 161 | ACLK_PERILP0_PLL_SEL_CPLL = 0, |
| 162 | ACLK_PERILP0_PLL_SEL_GPLL = 1, |
| 163 | ACLK_PERILP0_DIV_CON_MASK = 0x1f, |
| 164 | ACLK_PERILP0_DIV_CON_SHIFT = 0, |
| 165 | |
| 166 | /* CLKSEL_CON25 */ |
| 167 | PCLK_PERILP1_DIV_CON_MASK = 0x7, |
| 168 | PCLK_PERILP1_DIV_CON_SHIFT = 8, |
| 169 | HCLK_PERILP1_PLL_SEL_MASK = 1, |
| 170 | HCLK_PERILP1_PLL_SEL_SHIFT = 7, |
| 171 | HCLK_PERILP1_PLL_SEL_CPLL = 0, |
| 172 | HCLK_PERILP1_PLL_SEL_GPLL = 1, |
| 173 | HCLK_PERILP1_DIV_CON_MASK = 0x1f, |
| 174 | HCLK_PERILP1_DIV_CON_SHIFT = 0, |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 175 | |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 176 | /* CLKSEL_CON26 */ |
| 177 | CLK_SARADC_DIV_CON_MASK = 0xff, |
| 178 | CLK_SARADC_DIV_CON_SHIFT = 8, |
| 179 | |
Shunqian Zheng | f4181ce | 2016-05-06 16:50:48 +0800 | [diff] [blame] | 180 | /* CLKSEL_CON27 */ |
| 181 | CLK_TSADC_SEL_X24M = 0x0, |
| 182 | CLK_TSADC_SEL_MASK = 1, |
| 183 | CLK_TSADC_SEL_SHIFT = 15, |
| 184 | CLK_TSADC_DIV_CON_MASK = 0x3ff, |
| 185 | CLK_TSADC_DIV_CON_SHIFT = 0, |
| 186 | |
Lin Huang | 4ecccff | 2017-01-18 09:44:34 +0800 | [diff] [blame] | 187 | /* CLKSEL_CON44 */ |
| 188 | CLK_PCLK_EDP_PLL_SEL_MASK = 1, |
| 189 | CLK_PCLK_EDP_PLL_SEL_SHIFT = 15, |
| 190 | CLK_PCLK_EDP_PLL_SEL_CPLL = 0, |
| 191 | CLK_PCLK_EDP_DIV_CON_MASK = 0x3f, |
| 192 | CLK_PCLK_EDP_DIV_CON_SHIFT = 8, |
| 193 | |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 194 | /* CLKSEL_CON47 & CLKSEL_CON48 */ |
| 195 | ACLK_VOP_PLL_SEL_MASK = 0x3, |
| 196 | ACLK_VOP_PLL_SEL_SHIFT = 6, |
| 197 | ACLK_VOP_PLL_SEL_CPLL = 0x1, |
| 198 | ACLK_VOP_DIV_CON_MASK = 0x1f, |
| 199 | ACLK_VOP_DIV_CON_SHIFT = 0, |
| 200 | |
| 201 | /* CLKSEL_CON49 & CLKSEL_CON50 */ |
| 202 | DCLK_VOP_DCLK_SEL_MASK = 1, |
| 203 | DCLK_VOP_DCLK_SEL_SHIFT = 11, |
| 204 | DCLK_VOP_DCLK_SEL_DIVOUT = 0, |
| 205 | DCLK_VOP_PLL_SEL_MASK = 3, |
| 206 | DCLK_VOP_PLL_SEL_SHIFT = 8, |
| 207 | DCLK_VOP_PLL_SEL_VPLL = 0, |
| 208 | DCLK_VOP_DIV_CON_MASK = 0xff, |
| 209 | DCLK_VOP_DIV_CON_SHIFT = 0, |
| 210 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 211 | /* CLKSEL_CON58 */ |
| 212 | CLK_SPI_PLL_SEL_MASK = 1, |
| 213 | CLK_SPI_PLL_SEL_CPLL = 0, |
| 214 | CLK_SPI_PLL_SEL_GPLL = 1, |
| 215 | CLK_SPI_PLL_DIV_CON_MASK = 0x7f, |
| 216 | CLK_SPI5_PLL_DIV_CON_SHIFT = 8, |
| 217 | CLK_SPI5_PLL_SEL_SHIFT = 15, |
| 218 | |
| 219 | /* CLKSEL_CON59 */ |
| 220 | CLK_SPI1_PLL_SEL_SHIFT = 15, |
| 221 | CLK_SPI1_PLL_DIV_CON_SHIFT = 8, |
| 222 | CLK_SPI0_PLL_SEL_SHIFT = 7, |
| 223 | CLK_SPI0_PLL_DIV_CON_SHIFT = 0, |
| 224 | |
| 225 | /* CLKSEL_CON60 */ |
| 226 | CLK_SPI4_PLL_SEL_SHIFT = 15, |
| 227 | CLK_SPI4_PLL_DIV_CON_SHIFT = 8, |
| 228 | CLK_SPI2_PLL_SEL_SHIFT = 7, |
| 229 | CLK_SPI2_PLL_DIV_CON_SHIFT = 0, |
| 230 | |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 231 | /* CLKSEL_CON61 */ |
| 232 | CLK_I2C_PLL_SEL_MASK = 1, |
| 233 | CLK_I2C_PLL_SEL_CPLL = 0, |
| 234 | CLK_I2C_PLL_SEL_GPLL = 1, |
| 235 | CLK_I2C5_PLL_SEL_SHIFT = 15, |
| 236 | CLK_I2C5_DIV_CON_SHIFT = 8, |
| 237 | CLK_I2C1_PLL_SEL_SHIFT = 7, |
| 238 | CLK_I2C1_DIV_CON_SHIFT = 0, |
| 239 | |
| 240 | /* CLKSEL_CON62 */ |
| 241 | CLK_I2C6_PLL_SEL_SHIFT = 15, |
| 242 | CLK_I2C6_DIV_CON_SHIFT = 8, |
| 243 | CLK_I2C2_PLL_SEL_SHIFT = 7, |
| 244 | CLK_I2C2_DIV_CON_SHIFT = 0, |
| 245 | |
| 246 | /* CLKSEL_CON63 */ |
| 247 | CLK_I2C7_PLL_SEL_SHIFT = 15, |
| 248 | CLK_I2C7_DIV_CON_SHIFT = 8, |
| 249 | CLK_I2C3_PLL_SEL_SHIFT = 7, |
| 250 | CLK_I2C3_DIV_CON_SHIFT = 0, |
| 251 | |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 252 | /* CRU_SOFTRST_CON4 */ |
| 253 | RESETN_DDR0_REQ_MASK = 1, |
| 254 | RESETN_DDR0_REQ_SHIFT = 8, |
| 255 | RESETN_DDRPHY0_REQ_MASK = 1, |
| 256 | RESETN_DDRPHY0_REQ_SHIFT = 9, |
| 257 | RESETN_DDR1_REQ_MASK = 1, |
| 258 | RESETN_DDR1_REQ_SHIFT = 12, |
| 259 | RESETN_DDRPHY1_REQ_MASK = 1, |
| 260 | RESETN_DDRPHY1_REQ_SHIFT = 13, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 261 | }; |
| 262 | |
| 263 | #define VCO_MAX_KHZ (3200 * (MHz / KHz)) |
| 264 | #define VCO_MIN_KHZ (800 * (MHz / KHz)) |
| 265 | #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) |
| 266 | #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) |
| 267 | |
| 268 | /* the div restrictions of pll in integer mode, |
| 269 | * these are defined in * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 |
| 270 | */ |
| 271 | #define PLL_DIV_MIN 16 |
| 272 | #define PLL_DIV_MAX 3200 |
| 273 | |
| 274 | /* How to calculate the PLL(from TRM V0.3 Part 1 Page 63): |
| 275 | * Formulas also embedded within the Fractional PLL Verilog model: |
| 276 | * If DSMPD = 1 (DSM is disabled, "integer mode") |
| 277 | * FOUTVCO = FREF / REFDIV * FBDIV |
| 278 | * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 |
| 279 | * Where: |
| 280 | * FOUTVCO = Fractional PLL non-divided output frequency |
| 281 | * FOUTPOSTDIV = Fractional PLL divided output frequency |
| 282 | * (output of second post divider) |
| 283 | * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) |
| 284 | * REFDIV = Fractional PLL input reference clock divider |
| 285 | * FBDIV = Integer value programmed into feedback divide |
| 286 | * |
| 287 | */ |
| 288 | static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) |
| 289 | { |
| 290 | /* All 8 PLLs have same VCO and output frequency range restrictions. */ |
| 291 | u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; |
| 292 | u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; |
| 293 | |
| 294 | printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " |
Elyes HAOUAS | 8d1b0f1 | 2020-02-20 18:20:57 +0100 | [diff] [blame] | 295 | "postdiv2=%d, vco=%u kHz, output=%u kHz\n", |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 296 | pll_con, div->fbdiv, div->refdiv, div->postdiv1, |
| 297 | div->postdiv2, vco_khz, output_khz); |
| 298 | assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && |
| 299 | output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && |
| 300 | div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); |
| 301 | |
| 302 | /* When power on or changing PLL setting, |
| 303 | * we must force PLL into slow mode to ensure output stable clock. |
| 304 | */ |
| 305 | write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT, |
| 306 | PLL_MODE_SLOW << PLL_MODE_SHIFT)); |
| 307 | |
| 308 | /* use integer mode */ |
| 309 | write32(&pll_con[3], |
| 310 | RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, |
| 311 | PLL_INTEGER_MODE << PLL_DSMPD_SHIFT)); |
| 312 | |
| 313 | write32(&pll_con[0], RK_CLRSETBITS(PLL_FBDIV_MASK << PLL_FBDIV_SHIFT, |
| 314 | div->fbdiv << PLL_FBDIV_SHIFT)); |
| 315 | write32(&pll_con[1], |
| 316 | RK_CLRSETBITS(PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | |
| 317 | PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | |
| 318 | PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, |
| 319 | (div->postdiv2 << PLL_POSTDIV2_SHIFT) | |
| 320 | (div->postdiv1 << PLL_POSTDIV1_SHIFT) | |
| 321 | (div->refdiv << PLL_REFDIV_SHIFT))); |
| 322 | |
| 323 | /* waiting for pll lock */ |
| 324 | while (!(read32(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) |
| 325 | udelay(1); |
| 326 | |
| 327 | /* pll enter normal mode */ |
| 328 | write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT, |
| 329 | PLL_MODE_NORM << PLL_MODE_SHIFT)); |
| 330 | } |
| 331 | |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 332 | /* |
| 333 | * Configure the DPLL spread spectrum feature on memory clock. |
| 334 | * Configure sequence: |
Martin Roth | 9641a92 | 2018-05-20 17:46:51 -0600 | [diff] [blame] | 335 | * 1. PLL been configured as frac mode, and DACPD should be set to 1'b0. |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 336 | * 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with |
| 337 | * extern wave table). |
Martin Roth | 9641a92 | 2018-05-20 17:46:51 -0600 | [diff] [blame] | 338 | * 3. set ssmod_disable_sscg = 1'b0, and set ssmod_bp = 1'b0. |
| 339 | * 4. Assert RESET = 1'b1 to SSMOD. |
| 340 | * 5. RESET = 1'b0 on SSMOD. |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 341 | * 6. Adjust SPREAD/DIVVAL/DOWNSPREAD. |
| 342 | */ |
| 343 | static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) |
| 344 | { |
| 345 | u32 divval; |
| 346 | |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 347 | assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6); |
| 348 | |
| 349 | /* |
| 350 | * Need to acquire ~30kHZ which is the target modulation frequency. |
| 351 | * The modulation frequency ~ 30kHz= OSC_HZ/revdiv/128/divval |
| 352 | * (the 128 is the number points in the query table). |
| 353 | */ |
| 354 | divval = OSC_HZ / 128 / (30 * KHz) / dpll_cfg->refdiv; |
| 355 | |
| 356 | /* |
| 357 | * Use frac mode. |
| 358 | * Make sure the output frequency isn't offset, set 0 for Fractional |
| 359 | * part of feedback divide. |
| 360 | */ |
| 361 | write32(&cru_ptr->dpll_con[3], |
| 362 | RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, |
| 363 | PLL_FRAC_MODE << PLL_DSMPD_SHIFT)); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 364 | clrsetbits32(&cru_ptr->dpll_con[2], |
| 365 | PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, |
| 366 | 0 << PLL_FRACDIV_SHIFT); |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 367 | |
| 368 | /* |
| 369 | * Configure SSC divval. |
| 370 | * Spread amplitude range = 0.1 * SPREAD[4:0] (%). |
| 371 | * The below 8 means SPREAD[4:0] that appears to mitigate EMI on boards |
| 372 | * tested. Center and down spread modulation amplitudes based on the |
| 373 | * value of SPREAD. |
| 374 | * SPREAD[4:0] Center Spread Down Spread |
| 375 | * 0 0 0 |
Martin Roth | 9641a92 | 2018-05-20 17:46:51 -0600 | [diff] [blame] | 376 | * 1 +/-0.1% -0.10% |
| 377 | * 2 +/-0.2% -0.20% |
| 378 | * 3 +/-0.3% -0.30% |
| 379 | * 4 +/-0.4% -0.40% |
| 380 | * 5 +/-0.5% -0.50% |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 381 | * ... |
Martin Roth | 9641a92 | 2018-05-20 17:46:51 -0600 | [diff] [blame] | 382 | * 31 +/-3.1% -3.10% |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 383 | */ |
| 384 | write32(&cru_ptr->dpll_con[4], |
| 385 | RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT, |
| 386 | divval << PLL_SSMOD_DIVVAL_SHIFT)); |
| 387 | write32(&cru_ptr->dpll_con[4], |
| 388 | RK_CLRSETBITS(PLL_SSMOD_SPREADAMP_MASK << |
| 389 | PLL_SSMOD_SPREADAMP_SHIFT, |
| 390 | 8 << PLL_SSMOD_SPREADAMP_SHIFT)); |
| 391 | |
| 392 | /* Enable SSC for DPLL */ |
| 393 | write32(&cru_ptr->dpll_con[4], |
| 394 | RK_CLRBITS(PLL_SSMOD_BP_MASK << PLL_SSMOD_BP_SHIFT | |
| 395 | PLL_SSMOD_DIS_SSCG_MASK << PLL_SSMOD_DIS_SSCG_SHIFT)); |
| 396 | |
| 397 | /* Deassert reset SSMOD */ |
| 398 | write32(&cru_ptr->dpll_con[4], |
| 399 | RK_CLRBITS(PLL_SSMOD_RESET_MASK << PLL_SSMOD_RESET_SHIFT)); |
| 400 | |
| 401 | udelay(20); |
| 402 | } |
| 403 | |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 404 | static int pll_para_config(u32 freq_hz, struct pll_div *div) |
| 405 | { |
| 406 | u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; |
| 407 | u32 postdiv1, postdiv2 = 1; |
| 408 | u32 fref_khz; |
| 409 | u32 diff_khz, best_diff_khz; |
| 410 | const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; |
| 411 | const u32 max_postdiv1 = 7, max_postdiv2 = 7; |
| 412 | u32 vco_khz; |
| 413 | u32 freq_khz = freq_hz / KHz; |
| 414 | |
| 415 | if (!freq_hz) { |
| 416 | printk(BIOS_ERR, "%s: the frequency can't be 0 Hz\n", __func__); |
| 417 | return -1; |
| 418 | } |
| 419 | |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 420 | postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 421 | if (postdiv1 > max_postdiv1) { |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 422 | postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); |
| 423 | postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 424 | } |
| 425 | |
| 426 | vco_khz = freq_khz * postdiv1 * postdiv2; |
| 427 | |
| 428 | if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || |
| 429 | postdiv2 > max_postdiv2) { |
| 430 | printk(BIOS_ERR, "%s: Cannot find out a supported VCO" |
| 431 | " for Frequency (%uHz).\n", __func__, freq_hz); |
| 432 | return -1; |
| 433 | } |
| 434 | |
| 435 | div->postdiv1 = postdiv1; |
| 436 | div->postdiv2 = postdiv2; |
| 437 | |
| 438 | best_diff_khz = vco_khz; |
| 439 | for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { |
| 440 | fref_khz = ref_khz / refdiv; |
| 441 | |
| 442 | fbdiv = vco_khz / fref_khz; |
| 443 | if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) |
| 444 | continue; |
| 445 | diff_khz = vco_khz - fbdiv * fref_khz; |
| 446 | if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { |
| 447 | fbdiv++; |
| 448 | diff_khz = fref_khz - diff_khz; |
| 449 | } |
| 450 | |
| 451 | if (diff_khz >= best_diff_khz) |
| 452 | continue; |
| 453 | |
| 454 | best_diff_khz = diff_khz; |
| 455 | div->refdiv = refdiv; |
| 456 | div->fbdiv = fbdiv; |
| 457 | } |
| 458 | |
| 459 | if (best_diff_khz > 4 * (MHz/KHz)) { |
| 460 | printk(BIOS_ERR, "%s: Failed to match output frequency %u, " |
| 461 | "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, |
| 462 | best_diff_khz * KHz); |
| 463 | return -1; |
| 464 | } |
| 465 | return 0; |
| 466 | } |
| 467 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 468 | void rkclk_init(void) |
| 469 | { |
| 470 | u32 aclk_div; |
| 471 | u32 hclk_div; |
| 472 | u32 pclk_div; |
| 473 | |
| 474 | /* some cru registers changed by bootrom, we'd better reset them to |
| 475 | * reset/default values described in TRM to avoid confusion in kernel. |
Elyes HAOUAS | 8d1b0f1 | 2020-02-20 18:20:57 +0100 | [diff] [blame] | 476 | * Please consider these three lines as a fix of bootrom bug. |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 477 | */ |
| 478 | write32(&cru_ptr->clksel_con[12], 0xffff4101); |
| 479 | write32(&cru_ptr->clksel_con[19], 0xffff033f); |
| 480 | write32(&cru_ptr->clksel_con[56], 0x00030003); |
| 481 | |
| 482 | /* configure pmu pll(ppll) */ |
| 483 | rkclk_set_pll(&pmucru_ptr->ppll_con[0], &ppll_init_cfg); |
| 484 | |
| 485 | /* configure pmu pclk */ |
| 486 | pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 487 | assert((unsigned int)(PPLL_HZ - (pclk_div + 1) * PMU_PCLK_HZ) <= pclk_div |
| 488 | && pclk_div <= 0x1f); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 489 | write32(&pmucru_ptr->pmucru_clksel[0], |
| 490 | RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT, |
| 491 | pclk_div << PMU_PCLK_DIV_CON_SHIFT)); |
| 492 | |
| 493 | /* configure gpll cpll */ |
| 494 | rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg); |
| 495 | rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg); |
| 496 | |
| 497 | /* configure perihp aclk, hclk, pclk */ |
| 498 | aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 499 | assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 500 | |
| 501 | hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; |
| 502 | assert((hclk_div + 1) * PERIHP_HCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 503 | PERIHP_ACLK_HZ && (hclk_div <= 0x3)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 504 | |
| 505 | pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; |
| 506 | assert((pclk_div + 1) * PERIHP_PCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 507 | PERIHP_ACLK_HZ && (pclk_div <= 0x7)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 508 | |
| 509 | write32(&cru_ptr->clksel_con[14], |
| 510 | RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK << |
| 511 | PCLK_PERIHP_DIV_CON_SHIFT | |
| 512 | HCLK_PERIHP_DIV_CON_MASK << |
| 513 | HCLK_PERIHP_DIV_CON_SHIFT | |
| 514 | ACLK_PERIHP_PLL_SEL_MASK << |
| 515 | ACLK_PERIHP_PLL_SEL_SHIFT | |
| 516 | ACLK_PERIHP_DIV_CON_MASK << |
| 517 | ACLK_PERIHP_DIV_CON_SHIFT, |
| 518 | pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | |
| 519 | hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | |
| 520 | ACLK_PERIHP_PLL_SEL_GPLL << |
| 521 | ACLK_PERIHP_PLL_SEL_SHIFT | |
| 522 | aclk_div << ACLK_PERIHP_DIV_CON_SHIFT)); |
| 523 | |
| 524 | /* configure perilp0 aclk, hclk, pclk */ |
| 525 | aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 526 | assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 527 | |
| 528 | hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; |
| 529 | assert((hclk_div + 1) * PERILP0_HCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 530 | PERILP0_ACLK_HZ && (hclk_div <= 0x3)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 531 | |
| 532 | pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; |
| 533 | assert((pclk_div + 1) * PERILP0_PCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 534 | PERILP0_ACLK_HZ && (pclk_div <= 0x7)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 535 | |
| 536 | write32(&cru_ptr->clksel_con[23], |
| 537 | RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK << |
| 538 | PCLK_PERILP0_DIV_CON_SHIFT | |
| 539 | HCLK_PERILP0_DIV_CON_MASK << |
| 540 | HCLK_PERILP0_DIV_CON_SHIFT | |
| 541 | ACLK_PERILP0_PLL_SEL_MASK << |
| 542 | ACLK_PERILP0_PLL_SEL_SHIFT | |
| 543 | ACLK_PERILP0_DIV_CON_MASK << |
| 544 | ACLK_PERILP0_DIV_CON_SHIFT, |
| 545 | pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | |
| 546 | hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | |
| 547 | ACLK_PERILP0_PLL_SEL_GPLL << |
| 548 | ACLK_PERILP0_PLL_SEL_SHIFT | |
| 549 | aclk_div << ACLK_PERILP0_DIV_CON_SHIFT)); |
| 550 | |
| 551 | /* perilp1 hclk select gpll as source */ |
| 552 | hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; |
| 553 | assert((hclk_div + 1) * PERILP1_HCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 554 | GPLL_HZ && (hclk_div <= 0x1f)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 555 | |
Julius Werner | f7d519c | 2016-09-02 23:48:10 -0700 | [diff] [blame] | 556 | pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; |
| 557 | assert((pclk_div + 1) * PERILP1_PCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 558 | PERILP1_HCLK_HZ && (pclk_div <= 0x7)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 559 | |
| 560 | write32(&cru_ptr->clksel_con[25], |
| 561 | RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << |
| 562 | PCLK_PERILP1_DIV_CON_SHIFT | |
| 563 | HCLK_PERILP1_DIV_CON_MASK << |
| 564 | HCLK_PERILP1_DIV_CON_SHIFT | |
| 565 | HCLK_PERILP1_PLL_SEL_MASK << |
| 566 | HCLK_PERILP1_PLL_SEL_SHIFT, |
| 567 | pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | |
| 568 | hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | |
| 569 | HCLK_PERILP1_PLL_SEL_GPLL << |
| 570 | HCLK_PERILP1_PLL_SEL_SHIFT)); |
| 571 | } |
| 572 | |
Julius Werner | 7f96589 | 2016-08-29 15:07:58 -0700 | [diff] [blame] | 573 | void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster) |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 574 | { |
Julius Werner | 7f96589 | 2016-08-29 15:07:58 -0700 | [diff] [blame] | 575 | u32 aclkm_div, atclk_div, pclk_dbg_div, apll_hz; |
| 576 | int con_base, parent; |
| 577 | u32 *pll_con; |
Lin Huang | e3d78b8 | 2016-06-28 11:10:54 +0800 | [diff] [blame] | 578 | |
Julius Werner | 7f96589 | 2016-08-29 15:07:58 -0700 | [diff] [blame] | 579 | switch (cluster) { |
| 580 | case CPU_CLUSTER_LITTLE: |
| 581 | con_base = 0; |
| 582 | parent = CLK_CORE_PLL_SEL_ALPLL; |
| 583 | pll_con = &cru_ptr->apll_l_con[0]; |
| 584 | break; |
| 585 | case CPU_CLUSTER_BIG: |
| 586 | default: |
| 587 | con_base = 2; |
| 588 | parent = CLK_CORE_PLL_SEL_ABPLL; |
| 589 | pll_con = &cru_ptr->apll_b_con[0]; |
| 590 | break; |
| 591 | } |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 592 | |
Julius Werner | 7f96589 | 2016-08-29 15:07:58 -0700 | [diff] [blame] | 593 | apll_hz = apll_cfgs[freq]->freq; |
| 594 | rkclk_set_pll(pll_con, apll_cfgs[freq]); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 595 | |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 596 | aclkm_div = DIV_ROUND_UP(apll_hz, ACLKM_CORE_HZ) - 1; |
| 597 | pclk_dbg_div = DIV_ROUND_UP(apll_hz, PCLK_DBG_HZ) - 1; |
| 598 | atclk_div = DIV_ROUND_UP(apll_hz, ATCLK_CORE_HZ) - 1; |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 599 | |
Lin Huang | bdd06de | 2016-06-28 15:21:20 +0800 | [diff] [blame] | 600 | write32(&cru_ptr->clksel_con[con_base], |
| 601 | RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK << |
| 602 | ACLKM_CORE_DIV_CON_SHIFT | |
| 603 | CLK_CORE_PLL_SEL_MASK << CLK_CORE_PLL_SEL_SHIFT | |
| 604 | CLK_CORE_DIV_MASK << CLK_CORE_DIV_SHIFT, |
| 605 | aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | |
| 606 | parent << CLK_CORE_PLL_SEL_SHIFT | |
| 607 | 0 << CLK_CORE_DIV_SHIFT)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 608 | |
Lin Huang | bdd06de | 2016-06-28 15:21:20 +0800 | [diff] [blame] | 609 | write32(&cru_ptr->clksel_con[con_base + 1], |
| 610 | RK_CLRSETBITS(PCLK_DBG_DIV_MASK << PCLK_DBG_DIV_SHIFT | |
| 611 | ATCLK_CORE_DIV_MASK << ATCLK_CORE_DIV_SHIFT, |
| 612 | pclk_dbg_div << PCLK_DBG_DIV_SHIFT | |
| 613 | atclk_div << ATCLK_CORE_DIV_SHIFT)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 614 | } |
Lin Huang | f5702e7 | 2016-03-19 22:45:19 +0800 | [diff] [blame] | 615 | |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 616 | void rkclk_configure_ddr(unsigned int hz) |
| 617 | { |
| 618 | struct pll_div dpll_cfg; |
| 619 | |
| 620 | /* IC ECO bug, need to set this register */ |
| 621 | write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xc000c000); |
| 622 | |
| 623 | /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ |
| 624 | switch (hz) { |
| 625 | case 200*MHz: |
| 626 | dpll_cfg = (struct pll_div) |
Caesar Wang | a0199d8 | 2017-06-22 16:14:58 +0800 | [diff] [blame] | 627 | {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}; |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 628 | break; |
| 629 | case 300*MHz: |
| 630 | dpll_cfg = (struct pll_div) |
| 631 | {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; |
| 632 | break; |
| 633 | case 666*MHz: |
| 634 | dpll_cfg = (struct pll_div) |
| 635 | {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; |
| 636 | break; |
| 637 | case 800*MHz: |
| 638 | dpll_cfg = (struct pll_div) |
| 639 | {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; |
| 640 | break; |
Lin Huang | ba2b63a | 2016-07-25 10:06:09 +0800 | [diff] [blame] | 641 | case 933*MHz: |
Shunqian Zheng | 0d9839b | 2016-05-11 15:18:17 +0800 | [diff] [blame] | 642 | dpll_cfg = (struct pll_div) |
Derek Basehore | 8e1a995 | 2016-10-27 13:51:49 -0700 | [diff] [blame] | 643 | {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; |
Shunqian Zheng | 0d9839b | 2016-05-11 15:18:17 +0800 | [diff] [blame] | 644 | break; |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 645 | default: |
| 646 | die("Unsupported SDRAM frequency, add to clock.c!"); |
| 647 | } |
| 648 | rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg); |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 649 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 650 | if (CONFIG(RK3399_SPREAD_SPECTRUM_DDR)) |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 651 | rkclk_set_dpllssc(&dpll_cfg); |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 652 | } |
| 653 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 654 | #define SPI_CLK_REG_VALUE(bus, clk_div) \ |
| 655 | RK_CLRSETBITS(CLK_SPI_PLL_SEL_MASK << \ |
| 656 | CLK_SPI ##bus## _PLL_SEL_SHIFT | \ |
| 657 | CLK_SPI_PLL_DIV_CON_MASK << \ |
| 658 | CLK_SPI ##bus## _PLL_DIV_CON_SHIFT, \ |
| 659 | CLK_SPI_PLL_SEL_GPLL << \ |
| 660 | CLK_SPI ##bus## _PLL_SEL_SHIFT | \ |
| 661 | (clk_div - 1) << \ |
| 662 | CLK_SPI ##bus## _PLL_DIV_CON_SHIFT) |
| 663 | |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 664 | void rkclk_configure_spi(unsigned int bus, unsigned int hz) |
| 665 | { |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 666 | int src_clk_div; |
| 667 | int pll; |
| 668 | |
| 669 | /* spi3 src clock from ppll, while spi0,1,2,4,5 src clock from gpll */ |
| 670 | pll = (bus == 3) ? PPLL_HZ : GPLL_HZ; |
| 671 | src_clk_div = pll / hz; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 672 | assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll)); |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 673 | |
| 674 | switch (bus) { |
| 675 | case 0: |
| 676 | write32(&cru_ptr->clksel_con[59], |
| 677 | SPI_CLK_REG_VALUE(0, src_clk_div)); |
| 678 | break; |
| 679 | case 1: |
| 680 | write32(&cru_ptr->clksel_con[59], |
| 681 | SPI_CLK_REG_VALUE(1, src_clk_div)); |
| 682 | break; |
| 683 | case 2: |
| 684 | write32(&cru_ptr->clksel_con[60], |
| 685 | SPI_CLK_REG_VALUE(2, src_clk_div)); |
| 686 | break; |
| 687 | case 3: |
| 688 | write32(&pmucru_ptr->pmucru_clksel[1], |
| 689 | RK_CLRSETBITS(SPI3_PLL_SEL_MASK << SPI3_PLL_SEL_SHIFT | |
| 690 | SPI3_DIV_CON_MASK << SPI3_DIV_CON_SHIFT, |
| 691 | SPI3_PLL_SEL_PPLL << SPI3_PLL_SEL_SHIFT | |
| 692 | (src_clk_div - 1) << SPI3_DIV_CON_SHIFT)); |
| 693 | break; |
| 694 | case 4: |
| 695 | write32(&cru_ptr->clksel_con[60], |
| 696 | SPI_CLK_REG_VALUE(4, src_clk_div)); |
| 697 | break; |
| 698 | case 5: |
| 699 | write32(&cru_ptr->clksel_con[58], |
| 700 | SPI_CLK_REG_VALUE(5, src_clk_div)); |
| 701 | break; |
| 702 | default: |
| 703 | printk(BIOS_ERR, "do not support this spi bus\n"); |
| 704 | } |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 705 | } |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 706 | |
| 707 | #define I2C_CLK_REG_VALUE(bus, clk_div) \ |
| 708 | RK_CLRSETBITS(I2C_DIV_CON_MASK << \ |
| 709 | CLK_I2C ##bus## _DIV_CON_SHIFT | \ |
| 710 | CLK_I2C_PLL_SEL_MASK << \ |
| 711 | CLK_I2C ##bus## _PLL_SEL_SHIFT, \ |
| 712 | (clk_div - 1) << \ |
| 713 | CLK_I2C ##bus## _DIV_CON_SHIFT | \ |
| 714 | CLK_I2C_PLL_SEL_GPLL << \ |
| 715 | CLK_I2C ##bus## _PLL_SEL_SHIFT) |
| 716 | #define PMU_I2C_CLK_REG_VALUE(bus, clk_div) \ |
| 717 | RK_CLRSETBITS(I2C_DIV_CON_MASK << I2C ##bus## _DIV_CON_SHIFT, \ |
| 718 | (clk_div - 1) << I2C ##bus## _DIV_CON_SHIFT) |
| 719 | |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 720 | uint32_t rkclk_i2c_clock_for_bus(unsigned int bus) |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 721 | { |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 722 | int src_clk_div, pll, freq; |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 723 | |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 724 | /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll */ |
| 725 | if (bus == 0 || bus == 4 || bus == 8) { |
| 726 | pll = PPLL_HZ; |
| 727 | freq = 338*MHz; |
| 728 | } else { |
| 729 | pll = GPLL_HZ; |
| 730 | freq = 198*MHz; |
| 731 | } |
| 732 | src_clk_div = pll / freq; |
| 733 | assert((src_clk_div - 1 <= 127) && (src_clk_div * freq == pll)); |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 734 | |
| 735 | switch (bus) { |
| 736 | case 0: |
| 737 | write32(&pmucru_ptr->pmucru_clksel[2], |
| 738 | PMU_I2C_CLK_REG_VALUE(0, src_clk_div)); |
| 739 | break; |
| 740 | case 1: |
| 741 | write32(&cru_ptr->clksel_con[61], |
| 742 | I2C_CLK_REG_VALUE(1, src_clk_div)); |
| 743 | break; |
| 744 | case 2: |
| 745 | write32(&cru_ptr->clksel_con[62], |
| 746 | I2C_CLK_REG_VALUE(2, src_clk_div)); |
| 747 | break; |
| 748 | case 3: |
| 749 | write32(&cru_ptr->clksel_con[63], |
| 750 | I2C_CLK_REG_VALUE(3, src_clk_div)); |
| 751 | break; |
| 752 | case 4: |
| 753 | write32(&pmucru_ptr->pmucru_clksel[3], |
| 754 | PMU_I2C_CLK_REG_VALUE(4, src_clk_div)); |
| 755 | break; |
| 756 | case 5: |
| 757 | write32(&cru_ptr->clksel_con[61], |
| 758 | I2C_CLK_REG_VALUE(5, src_clk_div)); |
| 759 | break; |
| 760 | case 6: |
| 761 | write32(&cru_ptr->clksel_con[62], |
| 762 | I2C_CLK_REG_VALUE(6, src_clk_div)); |
| 763 | break; |
| 764 | case 7: |
| 765 | write32(&cru_ptr->clksel_con[63], |
| 766 | I2C_CLK_REG_VALUE(7, src_clk_div)); |
| 767 | break; |
| 768 | case 8: |
| 769 | write32(&pmucru_ptr->pmucru_clksel[2], |
| 770 | PMU_I2C_CLK_REG_VALUE(8, src_clk_div)); |
| 771 | break; |
| 772 | default: |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 773 | die("unknown i2c bus\n"); |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 774 | } |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 775 | |
| 776 | return freq; |
| 777 | } |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 778 | |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 779 | static u32 clk_gcd(u32 a, u32 b) |
| 780 | { |
| 781 | while (b != 0) { |
| 782 | int r = b; |
| 783 | b = a % b; |
| 784 | a = r; |
| 785 | } |
| 786 | return a; |
| 787 | } |
| 788 | |
| 789 | void rkclk_configure_i2s(unsigned int hz) |
| 790 | { |
| 791 | int n, d; |
| 792 | int v; |
| 793 | |
| 794 | /** |
Elyes HAOUAS | 809aeee | 2018-08-07 12:14:33 +0200 | [diff] [blame] | 795 | * clk_i2s0_sel: divider output from fraction |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 796 | * clk_i2s0_pll_sel source clock: cpll |
| 797 | * clk_i2s0_div_con: 1 (div+1) |
| 798 | */ |
| 799 | write32(&cru_ptr->clksel_con[28], |
| 800 | RK_CLRSETBITS(3 << 8 | 1 << 7 | 0x7f << 0, |
| 801 | 1 << 8 | 0 << 7 | 0 << 0)); |
| 802 | |
| 803 | /* make sure and enable i2s0 path gates */ |
| 804 | write32(&cru_ptr->clkgate_con[8], |
| 805 | RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3)); |
| 806 | |
| 807 | /* set frac divider */ |
| 808 | v = clk_gcd(CPLL_HZ, hz); |
| 809 | n = (CPLL_HZ / v) & (0xffff); |
| 810 | d = (hz / v) & (0xffff); |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 811 | assert(hz == (u64)CPLL_HZ * d / n); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 812 | write32(&cru_ptr->clksel_con[96], d << 16 | n); |
| 813 | |
| 814 | /** |
| 815 | * clk_i2sout_sel clk_i2s |
| 816 | * clk_i2s_ch_sel: clk_i2s0 |
| 817 | */ |
| 818 | write32(&cru_ptr->clksel_con[31], |
| 819 | RK_CLRSETBITS(1 << 2 | 3 << 0, |
| 820 | 0 << 2 | 0 << 0)); |
| 821 | } |
| 822 | |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 823 | void rkclk_configure_saradc(unsigned int hz) |
| 824 | { |
| 825 | int src_clk_div; |
| 826 | |
| 827 | /* saradc src clk from 24MHz */ |
| 828 | src_clk_div = 24 * MHz / hz; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 829 | assert((src_clk_div - 1 <= 255) && (src_clk_div * hz == 24 * MHz)); |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 830 | |
| 831 | write32(&cru_ptr->clksel_con[26], |
| 832 | RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK << |
| 833 | CLK_SARADC_DIV_CON_SHIFT, |
| 834 | (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT)); |
| 835 | } |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 836 | |
| 837 | void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) |
| 838 | { |
| 839 | u32 div; |
| 840 | void *reg_addr = vop_id ? &cru_ptr->clksel_con[48] : |
| 841 | &cru_ptr->clksel_con[47]; |
| 842 | |
| 843 | /* vop aclk source clk: cpll */ |
| 844 | div = CPLL_HZ / aclk_hz; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 845 | assert((div - 1 <= 31) && (div * aclk_hz == CPLL_HZ)); |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 846 | |
| 847 | write32(reg_addr, RK_CLRSETBITS( |
| 848 | ACLK_VOP_PLL_SEL_MASK << ACLK_VOP_PLL_SEL_SHIFT | |
| 849 | ACLK_VOP_DIV_CON_MASK << ACLK_VOP_DIV_CON_SHIFT, |
| 850 | ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | |
| 851 | (div - 1) << ACLK_VOP_DIV_CON_SHIFT)); |
| 852 | } |
| 853 | |
| 854 | int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) |
| 855 | { |
| 856 | struct pll_div vpll_config = {0}; |
| 857 | void *reg_addr = vop_id ? &cru_ptr->clksel_con[50] : |
| 858 | &cru_ptr->clksel_con[49]; |
| 859 | |
| 860 | /* vop dclk source from vpll, and equals to vpll(means div == 1) */ |
| 861 | if (pll_para_config(dclk_hz, &vpll_config)) |
| 862 | return -1; |
| 863 | |
| 864 | rkclk_set_pll(&cru_ptr->vpll_con[0], &vpll_config); |
| 865 | |
| 866 | write32(reg_addr, RK_CLRSETBITS( |
| 867 | DCLK_VOP_DCLK_SEL_MASK << DCLK_VOP_DCLK_SEL_SHIFT | |
| 868 | DCLK_VOP_PLL_SEL_MASK << DCLK_VOP_PLL_SEL_SHIFT | |
| 869 | DCLK_VOP_DIV_CON_MASK << DCLK_VOP_DIV_CON_SHIFT, |
| 870 | DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | |
| 871 | DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | |
| 872 | (1 - 1) << DCLK_VOP_DIV_CON_SHIFT)); |
| 873 | |
| 874 | return 0; |
| 875 | } |
Shunqian Zheng | f4181ce | 2016-05-06 16:50:48 +0800 | [diff] [blame] | 876 | |
| 877 | void rkclk_configure_tsadc(unsigned int hz) |
| 878 | { |
| 879 | int src_clk_div; |
| 880 | |
| 881 | /* use 24M as src clock */ |
| 882 | src_clk_div = OSC_HZ / hz; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 883 | assert((src_clk_div - 1 <= 1023) && (src_clk_div * hz == OSC_HZ)); |
Shunqian Zheng | f4181ce | 2016-05-06 16:50:48 +0800 | [diff] [blame] | 884 | |
| 885 | write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS( |
| 886 | CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT | |
| 887 | CLK_TSADC_SEL_MASK << CLK_TSADC_SEL_SHIFT, |
| 888 | src_clk_div << CLK_TSADC_DIV_CON_SHIFT | |
| 889 | CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT)); |
| 890 | } |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 891 | |
| 892 | void rkclk_configure_emmc(void) |
| 893 | { |
| 894 | int src_clk_div; |
Ziyuan Xu | c53cf64 | 2016-09-18 10:49:52 +0800 | [diff] [blame] | 895 | int aclk_emmc = 148500*KHz; |
| 896 | int clk_emmc = 148500*KHz; |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 897 | |
| 898 | /* Select aclk_emmc source from GPLL */ |
| 899 | src_clk_div = GPLL_HZ / aclk_emmc; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 900 | assert((src_clk_div - 1 <= 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 901 | |
| 902 | write32(&cru_ptr->clksel_con[21], |
| 903 | RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK << |
| 904 | ACLK_EMMC_PLL_SEL_SHIFT | |
| 905 | ACLK_EMMC_DIV_CON_MASK << ACLK_EMMC_DIV_CON_SHIFT, |
| 906 | ACLK_EMMC_PLL_SEL_GPLL << |
| 907 | ACLK_EMMC_PLL_SEL_SHIFT | |
| 908 | (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT)); |
| 909 | |
| 910 | /* Select clk_emmc source from GPLL too */ |
| 911 | src_clk_div = GPLL_HZ / clk_emmc; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 912 | assert((src_clk_div - 1 <= 127) && (src_clk_div * clk_emmc == GPLL_HZ)); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 913 | |
| 914 | write32(&cru_ptr->clksel_con[22], |
| 915 | RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT | |
| 916 | CLK_EMMC_DIV_CON_MASK << CLK_EMMC_DIV_CON_SHIFT, |
| 917 | CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | |
| 918 | (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT)); |
| 919 | } |
Julius Werner | b6bf1dd | 2016-08-24 19:38:05 -0700 | [diff] [blame] | 920 | |
| 921 | int rkclk_was_watchdog_reset(void) |
| 922 | { |
| 923 | /* Bits 5 and 4 are "second" and "first" global watchdog reset. */ |
| 924 | return read32(&cru_ptr->glb_rst_st) & 0x30; |
| 925 | } |
Lin Huang | 4ecccff | 2017-01-18 09:44:34 +0800 | [diff] [blame] | 926 | |
| 927 | void rkclk_configure_edp(unsigned int hz) |
| 928 | { |
| 929 | int src_clk_div; |
| 930 | |
| 931 | src_clk_div = CPLL_HZ / hz; |
| 932 | assert((src_clk_div - 1 <= 63) && (src_clk_div * hz == CPLL_HZ)); |
| 933 | |
| 934 | write32(&cru_ptr->clksel_con[44], |
| 935 | RK_CLRSETBITS(CLK_PCLK_EDP_PLL_SEL_MASK << |
| 936 | CLK_PCLK_EDP_PLL_SEL_SHIFT | |
| 937 | CLK_PCLK_EDP_DIV_CON_MASK << |
| 938 | CLK_PCLK_EDP_DIV_CON_SHIFT, |
| 939 | CLK_PCLK_EDP_PLL_SEL_CPLL << |
| 940 | CLK_PCLK_EDP_PLL_SEL_SHIFT | |
| 941 | (src_clk_div - 1) << |
| 942 | CLK_PCLK_EDP_DIV_CON_SHIFT)); |
| 943 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 944 | |
| 945 | void rkclk_configure_mipi(void) |
| 946 | { |
| 947 | /* Enable clk_mipidphy_ref and clk_mipidphy_cfg */ |
| 948 | write32(&cru_ptr->clkgate_con[11], |
| 949 | RK_CLRBITS(1 << 14 | 1 << 15)); |
| 950 | /* Enable pclk_mipi_dsi0 */ |
| 951 | write32(&cru_ptr->clkgate_con[29], |
| 952 | RK_CLRBITS(1 << 1)); |
| 953 | } |