commit e3d78b82a76c6069a8111b278d4af57e9788ef9e
author Lin Huang <hl@rock-chips.com> Tue Jun 28 11:10:54 2016 +0800
committer Martin Roth <martinroth@google.com> Tue Jul 12 00:27:08 2016 +0200
tree 00337e51b9a8fddcc6db38ee8dd15536a5b534a6
parent 9e624fc27f123c8b5eb6ef5a1ecd57facca16a7f

rockchip/rk3399: calculate clocks based on parent clock speed

Currently aclkm pclkdbg atclk clocks use apll_l as a parent, but the
apll_l frequency may change in firmware, so we need to caculate the div
value based on the apll_l frequency.

BRANCH=None
BUG=chrome-os-partner:54376
TEST=Boot from Gru

Change-Id: I2bd8886168453ce98efec58b5490c2430762769b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 116ae863a504630e2aff056564836d84198fcae2
Original-Change-Id: I7e3a5d9e3f608ddf15592d893117c92767fcd015
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/356397
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15581
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/rockchip/rk3399/clock.c

diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 6d40cd2..8b27454 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -31,12 +31,13 @@
 	u32 postdiv1;
 	u32 postdiv2;
 	u32 frac;
+	u32 freq;
 };
 
 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
 	.refdiv = _refdiv,\
 	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
-	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
+	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};\
 	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
 			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
 			 #hz "Hz cannot be hit with PLL "\
@@ -491,20 +492,17 @@
 	u32 aclkm_div;
 	u32 pclk_dbg_div;
 	u32 atclk_div;
+	u32 apll_l_hz;
+
+	apll_l_hz = apll_l_cfgs[apll_l_freq]->freq;
 
 	rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
 
-	aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1;
-	assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ &&
-	       aclkm_div < 0x1f);
+	aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1;
 
-	pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1;
-	assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ &&
-	       pclk_dbg_div < 0x1f);
+	pclk_dbg_div = div_round_up(apll_l_hz, PCLK_DBG_HZ) - 1;
 
-	atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1;
-	assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ &&
-	       atclk_div < 0x1f);
+	atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1;
 
 	write32(&cru_ptr->clksel_con[0],
 		RK_CLRSETBITS(ACLKM_CORE_L_DIV_CON_MASK <<