rockchip: rk3399: support saradc
This patch add functions to configure saradc clk and get
saradc's raw value for each channel.
Currently add saradc to ramstage.
Please refer to TRM V0.3 Part 2 Chapter 18 for this IP.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=on kevin board, get the raw value 61 for channel 0,
measure the ADC_IN0 as 0.109V,
61.0/1024 = 0.05957 0.109V/1.8V = 0.06056
Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a
Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/334177
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14720
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index d706c93..1050552 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -155,6 +155,10 @@
HCLK_PERILP1_DIV_CON_MASK = 0x1f,
HCLK_PERILP1_DIV_CON_SHIFT = 0,
+ /* CLKSEL_CON26 */
+ CLK_SARADC_DIV_CON_MASK = 0xff,
+ CLK_SARADC_DIV_CON_SHIFT = 8,
+
/* CLKSEL_CON58 */
CLK_SPI_PLL_SEL_MASK = 1,
CLK_SPI_PLL_SEL_CPLL = 0,
@@ -575,3 +579,17 @@
return freq;
}
+
+void rkclk_configure_saradc(unsigned int hz)
+{
+ int src_clk_div;
+
+ /* saradc src clk from 24MHz */
+ src_clk_div = 24 * MHz / hz;
+ assert((src_clk_div - 1 < 255) && (src_clk_div * hz == 24 * MHz));
+
+ write32(&cru_ptr->clksel_con[26],
+ RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK <<
+ CLK_SARADC_DIV_CON_SHIFT,
+ (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT));
+}