blob: dd53deba9c724b902778896ce7124ce852aea974 [file] [log] [blame]
Angel Ponsba38f372020-04-05 15:46:45 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Lee Leahy77ff0b12015-05-05 15:07:29 -07003
Lee Leahy77ff0b12015-05-05 15:07:29 -07004#include <cpu/x86/msr.h>
5#include <cpu/x86/tsc.h>
6#include <soc/msr.h>
Lee Leahy32471722015-04-20 15:20:28 -07007#include <stdint.h>
8
Subrata Banik45a221d2015-08-05 17:01:55 +05309static const unsigned int cpu_bus_clk_freq_table[] = {
10 83333,
11 100000,
12 133333,
13 116666,
14 80000,
15 93333,
16 90000,
17 88900,
18 87500
19};
20
21unsigned int cpu_bus_freq_khz(void)
22{
23 msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
Angel Ponsaee7ab22020-03-19 00:31:58 +010024
25 if ((clk_info.lo & 0xf) < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int)))
26 return cpu_bus_clk_freq_table[clk_info.lo & 0xf];
27
Subrata Banik45a221d2015-08-05 17:01:55 +053028 return 0;
29}
30
Lee Leahy32471722015-04-20 15:20:28 -070031unsigned long tsc_freq_mhz(void)
32{
Subrata Banik45a221d2015-08-05 17:01:55 +053033 msr_t platform_info;
34 unsigned int bclk_khz = cpu_bus_freq_khz();
Lee Leahy32471722015-04-20 15:20:28 -070035
Subrata Banik45a221d2015-08-05 17:01:55 +053036 if (!bclk_khz)
37 return 0;
38
39 platform_info = rdmsr(MSR_PLATFORM_INFO);
40 return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
Lee Leahy32471722015-04-20 15:20:28 -070041}
42
Lee Leahy77ff0b12015-05-05 15:07:29 -070043void set_max_freq(void)
44{
45 msr_t perf_ctl;
46 msr_t msr;
47
Angel Ponsaee7ab22020-03-19 00:31:58 +010048 /* Enable Intel SpeedStep */
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020049 msr = rdmsr(IA32_MISC_ENABLE);
Lee Leahy77ff0b12015-05-05 15:07:29 -070050 msr.lo |= (1 << 16);
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020051 wrmsr(IA32_MISC_ENABLE, msr);
Lee Leahy77ff0b12015-05-05 15:07:29 -070052
Hannah Williamsb0eb5942015-08-23 17:24:43 -070053 /* Enable Burst Mode */
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020054 msr = rdmsr(IA32_MISC_ENABLE);
Hannah Williamsb0eb5942015-08-23 17:24:43 -070055 msr.hi = 0;
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020056 wrmsr(IA32_MISC_ENABLE, msr);
Hannah Williamsb0eb5942015-08-23 17:24:43 -070057
Angel Ponsaee7ab22020-03-19 00:31:58 +010058 /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of the PERF_CTL */
Hannah Williamsb0eb5942015-08-23 17:24:43 -070059 msr = rdmsr(MSR_IACORE_TURBO_RATIOS);
Angel Ponsaee7ab22020-03-19 00:31:58 +010060 perf_ctl.lo = (msr.lo & 0x003f0000) >> 8;
Lee Leahy32471722015-04-20 15:20:28 -070061
Angel Ponsaee7ab22020-03-19 00:31:58 +010062 /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of the PERF_CTL */
Hannah Williamsb0eb5942015-08-23 17:24:43 -070063 msr = rdmsr(MSR_IACORE_TURBO_VIDS);
Angel Ponsaee7ab22020-03-19 00:31:58 +010064 perf_ctl.lo |= (msr.lo & 0x007f0000) >> 16;
Lee Leahy77ff0b12015-05-05 15:07:29 -070065 perf_ctl.hi = 0;
66
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020067 wrmsr(IA32_PERF_CTL, perf_ctl);
Lee Leahy77ff0b12015-05-05 15:07:29 -070068}