blob: 700b0985caf74a7b2935a3bc36f9ffcf1eabe13a [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <stdint.h>
21#include <cpu/x86/msr.h>
22#include <cpu/x86/tsc.h>
23#include <soc/msr.h>
24
25unsigned bus_freq_khz(void)
26{
27 msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
28 switch (clk_info.lo & 0x3) {
29 case 0:
30 return 83333;
31 case 1:
32 return 100000;
33 case 2:
34 return 133333;
35 case 3:
36 return 116666;
37 default:
38 return 0;
39 }
40}
41
42unsigned long tsc_freq_mhz(void)
43{
44 msr_t platform_info;
45 unsigned bclk_khz = bus_freq_khz();
46
47 if (!bclk_khz)
48 return 0;
49
50 platform_info = rdmsr(MSR_PLATFORM_INFO);
51 return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
52}
53
54#if !defined(__SMM__)
55#if !defined(__PRE_RAM__)
56#include <soc/ramstage.h>
57#else
58#include <soc/romstage.h>
59#endif
60
61void set_max_freq(void)
62{
63 msr_t perf_ctl;
64 msr_t msr;
65
66 /* Enable speed step. */
67 msr = rdmsr(MSR_IA32_MISC_ENABLES);
68 msr.lo |= (1 << 16);
69 wrmsr(MSR_IA32_MISC_ENABLES, msr);
70
71 /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
72 * the PERF_CTL. */
73 msr = rdmsr(MSR_IACORE_RATIOS);
74 perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
75 /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
76 * the PERF_CTL. */
77 msr = rdmsr(MSR_IACORE_VIDS);
78 perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
79 perf_ctl.hi = 0;
80
81 wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
82}
83
84#endif /* __SMM__ */