src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.
Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index b05a007..72dbca5 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -67,14 +67,14 @@
msr_t msr;
/* Enable speed step. */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 16);
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/* Enable Burst Mode */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.hi = 0;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/*
* Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
@@ -91,7 +91,7 @@
perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
perf_ctl.hi = 0;
- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
+ wrmsr(IA32_PERF_CTL, perf_ctl);
}
#endif /* ENV_SMM */