blob: fff882eb9b4da4d03784e7ce6fabeadbf21b4381 [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy77ff0b12015-05-05 15:07:29 -070017#include <cpu/x86/msr.h>
18#include <cpu/x86/tsc.h>
Lee Leahyacb9c0b2015-07-02 11:55:18 -070019#include <rules.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070020#include <soc/msr.h>
Lee Leahy32471722015-04-20 15:20:28 -070021#include <console/console.h>
22#if ENV_RAMSTAGE
Lee Leahy77ff0b12015-05-05 15:07:29 -070023#include <soc/ramstage.h>
24#else
25#include <soc/romstage.h>
26#endif
Lee Leahy32471722015-04-20 15:20:28 -070027#include <stdint.h>
28
Subrata Banik45a221d2015-08-05 17:01:55 +053029static const unsigned int cpu_bus_clk_freq_table[] = {
30 83333,
31 100000,
32 133333,
33 116666,
34 80000,
35 93333,
36 90000,
37 88900,
38 87500
39};
40
41unsigned int cpu_bus_freq_khz(void)
42{
43 msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
44 if((clk_info.lo & 0xF) < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int)))
45 {
46 return(cpu_bus_clk_freq_table[clk_info.lo & 0xF]);
47 }
48 return 0;
49}
50
Lee Leahy32471722015-04-20 15:20:28 -070051unsigned long tsc_freq_mhz(void)
52{
Subrata Banik45a221d2015-08-05 17:01:55 +053053 msr_t platform_info;
54 unsigned int bclk_khz = cpu_bus_freq_khz();
Lee Leahy32471722015-04-20 15:20:28 -070055
Subrata Banik45a221d2015-08-05 17:01:55 +053056 if (!bclk_khz)
57 return 0;
58
59 platform_info = rdmsr(MSR_PLATFORM_INFO);
60 return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
Lee Leahy32471722015-04-20 15:20:28 -070061}
62
Lee Leahyacb9c0b2015-07-02 11:55:18 -070063#if !ENV_SMM
Lee Leahy77ff0b12015-05-05 15:07:29 -070064
65void set_max_freq(void)
66{
67 msr_t perf_ctl;
68 msr_t msr;
69
70 /* Enable speed step. */
71 msr = rdmsr(MSR_IA32_MISC_ENABLES);
72 msr.lo |= (1 << 16);
73 wrmsr(MSR_IA32_MISC_ENABLES, msr);
74
Lee Leahy32471722015-04-20 15:20:28 -070075 /*
76 * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
77 * the PERF_CTL.
78 */
Lee Leahy77ff0b12015-05-05 15:07:29 -070079 msr = rdmsr(MSR_IACORE_RATIOS);
80 perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
Lee Leahy32471722015-04-20 15:20:28 -070081
82 /*
83 * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
84 * the PERF_CTL.
85 */
Lee Leahy77ff0b12015-05-05 15:07:29 -070086 msr = rdmsr(MSR_IACORE_VIDS);
87 perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
88 perf_ctl.hi = 0;
89
90 wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
91}
92
Lee Leahyacb9c0b2015-07-02 11:55:18 -070093#endif /* ENV_SMM */