Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.
BRANCH=none
BUG=None
TEST=Build for a Braswell platform
Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index e5129d8..e7a1c13 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,46 +18,26 @@
* Foundation, Inc.
*/
-#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <soc/msr.h>
-
-unsigned bus_freq_khz(void)
-{
- msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
- switch (clk_info.lo & 0x3) {
- case 0:
- return 83333;
- case 1:
- return 100000;
- case 2:
- return 133333;
- case 3:
- return 116666;
- default:
- return 0;
- }
-}
-
-unsigned long tsc_freq_mhz(void)
-{
- msr_t platform_info;
- unsigned bclk_khz = bus_freq_khz();
-
- if (!bclk_khz)
- return 0;
-
- platform_info = rdmsr(MSR_PLATFORM_INFO);
- return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
-}
-
-#if !defined(__SMM__)
-#if !defined(__PRE_RAM__)
+#include <console/console.h>
+#if ENV_RAMSTAGE
#include <soc/ramstage.h>
#else
#include <soc/romstage.h>
#endif
+#include <stdint.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t ia_core_ratios;
+
+ ia_core_ratios = rdmsr(MSR_IACORE_RATIOS);
+ return (BUS_FREQ_KHZ * ((ia_core_ratios.lo >> 16) & 0x3f)) / 1000;
+}
+
+#if !defined(__SMM__)
void set_max_freq(void)
{
@@ -68,12 +49,17 @@
msr.lo |= (1 << 16);
wrmsr(MSR_IA32_MISC_ENABLES, msr);
- /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
- * the PERF_CTL. */
+ /*
+ * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
+ * the PERF_CTL.
+ */
msr = rdmsr(MSR_IACORE_RATIOS);
perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
- /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
- * the PERF_CTL. */
+
+ /*
+ * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
+ * the PERF_CTL.
+ */
msr = rdmsr(MSR_IACORE_VIDS);
perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
perf_ctl.hi = 0;