huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 16 | #include <assert.h> |
| 17 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 18 | #include <device/mmio.h> |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 19 | #include <delay.h> |
| 20 | #include <soc/addressmap.h> |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 21 | #include <soc/clock.h> |
Lin Huang | f5702e7 | 2016-03-19 22:45:19 +0800 | [diff] [blame] | 22 | #include <soc/grf.h> |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 23 | #include <soc/i2c.h> |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 24 | #include <soc/soc.h> |
| 25 | #include <stdint.h> |
| 26 | #include <stdlib.h> |
| 27 | #include <string.h> |
| 28 | |
| 29 | struct pll_div { |
| 30 | u32 refdiv; |
| 31 | u32 fbdiv; |
| 32 | u32 postdiv1; |
| 33 | u32 postdiv2; |
| 34 | u32 frac; |
Lin Huang | e3d78b8 | 2016-06-28 11:10:54 +0800 | [diff] [blame] | 35 | u32 freq; |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 36 | }; |
| 37 | |
| 38 | #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ |
| 39 | .refdiv = _refdiv,\ |
| 40 | .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ |
Lin Huang | e3d78b8 | 2016-06-28 11:10:54 +0800 | [diff] [blame] | 41 | .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};\ |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 42 | _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ |
| 43 | OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 44 | STRINGIFY(hz) " Hz cannot be hit with PLL "\ |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 45 | "divisors on line " STRINGIFY(__LINE__)) |
| 46 | |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 47 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); |
| 48 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 3, 1); |
| 49 | static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 3, 2, 1); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 50 | |
Eric Gao | 61e6c44 | 2016-07-29 12:34:32 +0800 | [diff] [blame] | 51 | static const struct pll_div apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1); |
| 52 | static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 53 | |
Lin Huang | 3d703bc | 2016-06-28 14:19:18 +0800 | [diff] [blame] | 54 | static const struct pll_div *apll_cfgs[] = { |
Eric Gao | 61e6c44 | 2016-07-29 12:34:32 +0800 | [diff] [blame] | 55 | [APLL_1512_MHZ] = &apll_1512_cfg, |
Lin Huang | 3d703bc | 2016-06-28 14:19:18 +0800 | [diff] [blame] | 56 | [APLL_600_MHZ] = &apll_600_cfg, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | enum { |
| 60 | /* PLL_CON0 */ |
| 61 | PLL_FBDIV_MASK = 0xfff, |
| 62 | PLL_FBDIV_SHIFT = 0, |
| 63 | |
| 64 | /* PLL_CON1 */ |
| 65 | PLL_POSTDIV2_MASK = 0x7, |
| 66 | PLL_POSTDIV2_SHIFT = 12, |
| 67 | PLL_POSTDIV1_MASK = 0x7, |
| 68 | PLL_POSTDIV1_SHIFT = 8, |
| 69 | PLL_REFDIV_MASK = 0x3f, |
| 70 | PLL_REFDIV_SHIFT = 0, |
| 71 | |
| 72 | /* PLL_CON2 */ |
| 73 | PLL_LOCK_STATUS_MASK = 1, |
| 74 | PLL_LOCK_STATUS_SHIFT = 31, |
| 75 | PLL_FRACDIV_MASK = 0xffffff, |
| 76 | PLL_FRACDIV_SHIFT = 0, |
| 77 | |
| 78 | /* PLL_CON3 */ |
| 79 | PLL_MODE_MASK = 3, |
| 80 | PLL_MODE_SHIFT = 8, |
| 81 | PLL_MODE_SLOW = 0, |
| 82 | PLL_MODE_NORM, |
| 83 | PLL_MODE_DEEP, |
| 84 | PLL_DSMPD_MASK = 1, |
| 85 | PLL_DSMPD_SHIFT = 3, |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 86 | PLL_FRAC_MODE = 0, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 87 | PLL_INTEGER_MODE = 1, |
| 88 | |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 89 | /* PLL_CON4 */ |
| 90 | PLL_SSMOD_BP_MASK = 1, |
| 91 | PLL_SSMOD_BP_SHIFT = 0, |
| 92 | PLL_SSMOD_DIS_SSCG_MASK = 1, |
| 93 | PLL_SSMOD_DIS_SSCG_SHIFT = 1, |
| 94 | PLL_SSMOD_RESET_MASK = 1, |
| 95 | PLL_SSMOD_RESET_SHIFT = 2, |
| 96 | PLL_SSMOD_DOWNSPEAD_MASK = 1, |
| 97 | PLL_SSMOD_DOWNSPEAD_SHIFT = 3, |
| 98 | PLL_SSMOD_DIVVAL_MASK = 0Xf, |
| 99 | PLL_SSMOD_DIVVAL_SHIFT = 4, |
| 100 | PLL_SSMOD_SPREADAMP_MASK = 0x1f, |
| 101 | PLL_SSMOD_SPREADAMP_SHIFT = 8, |
| 102 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 103 | /* PMUCRU_CLKSEL_CON0 */ |
| 104 | PMU_PCLK_DIV_CON_MASK = 0x1f, |
| 105 | PMU_PCLK_DIV_CON_SHIFT = 0, |
| 106 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 107 | /* PMUCRU_CLKSEL_CON1 */ |
| 108 | SPI3_PLL_SEL_MASK = 1, |
| 109 | SPI3_PLL_SEL_SHIFT = 7, |
| 110 | SPI3_PLL_SEL_24M = 0, |
| 111 | SPI3_PLL_SEL_PPLL = 1, |
| 112 | SPI3_DIV_CON_MASK = 0x7f, |
| 113 | SPI3_DIV_CON_SHIFT = 0x0, |
| 114 | |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 115 | /* PMUCRU_CLKSEL_CON2 */ |
| 116 | I2C_DIV_CON_MASK = 0x7f, |
| 117 | I2C8_DIV_CON_SHIFT = 8, |
| 118 | I2C0_DIV_CON_SHIFT = 0, |
| 119 | |
| 120 | /* PMUCRU_CLKSEL_CON3 */ |
| 121 | I2C4_DIV_CON_SHIFT = 0, |
| 122 | |
Lin Huang | bdd06de | 2016-06-28 15:21:20 +0800 | [diff] [blame] | 123 | /* CLKSEL_CON0 / CLKSEL_CON2 */ |
| 124 | ACLKM_CORE_DIV_CON_MASK = 0x1f, |
| 125 | ACLKM_CORE_DIV_CON_SHIFT = 8, |
| 126 | CLK_CORE_PLL_SEL_MASK = 3, |
| 127 | CLK_CORE_PLL_SEL_SHIFT = 6, |
| 128 | CLK_CORE_PLL_SEL_ALPLL = 0x0, |
| 129 | CLK_CORE_PLL_SEL_ABPLL = 0x1, |
| 130 | CLK_CORE_PLL_SEL_DPLL = 0x10, |
| 131 | CLK_CORE_PLL_SEL_GPLL = 0x11, |
| 132 | CLK_CORE_DIV_MASK = 0x1f, |
| 133 | CLK_CORE_DIV_SHIFT = 0, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 134 | |
Lin Huang | bdd06de | 2016-06-28 15:21:20 +0800 | [diff] [blame] | 135 | /* CLKSEL_CON1 / CLKSEL_CON3 */ |
| 136 | PCLK_DBG_DIV_MASK = 0x1f, |
| 137 | PCLK_DBG_DIV_SHIFT = 0x8, |
| 138 | ATCLK_CORE_DIV_MASK = 0x1f, |
| 139 | ATCLK_CORE_DIV_SHIFT = 0, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 140 | |
| 141 | /* CLKSEL_CON14 */ |
| 142 | PCLK_PERIHP_DIV_CON_MASK = 0x7, |
| 143 | PCLK_PERIHP_DIV_CON_SHIFT = 12, |
| 144 | HCLK_PERIHP_DIV_CON_MASK = 3, |
| 145 | HCLK_PERIHP_DIV_CON_SHIFT = 8, |
| 146 | ACLK_PERIHP_PLL_SEL_MASK = 1, |
| 147 | ACLK_PERIHP_PLL_SEL_SHIFT = 7, |
| 148 | ACLK_PERIHP_PLL_SEL_CPLL = 0, |
| 149 | ACLK_PERIHP_PLL_SEL_GPLL = 1, |
| 150 | ACLK_PERIHP_DIV_CON_MASK = 0x1f, |
| 151 | ACLK_PERIHP_DIV_CON_SHIFT = 0, |
| 152 | |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 153 | /* CLKSEL_CON21 */ |
| 154 | ACLK_EMMC_PLL_SEL_MASK = 0x1, |
| 155 | ACLK_EMMC_PLL_SEL_SHIFT = 7, |
| 156 | ACLK_EMMC_PLL_SEL_GPLL = 0x1, |
| 157 | ACLK_EMMC_DIV_CON_MASK = 0x1f, |
| 158 | ACLK_EMMC_DIV_CON_SHIFT = 0, |
| 159 | |
| 160 | /* CLKSEL_CON22 */ |
| 161 | CLK_EMMC_PLL_MASK = 0x7, |
| 162 | CLK_EMMC_PLL_SHIFT = 8, |
| 163 | CLK_EMMC_PLL_SEL_GPLL = 0x1, |
| 164 | CLK_EMMC_DIV_CON_MASK = 0x7f, |
| 165 | CLK_EMMC_DIV_CON_SHIFT = 0, |
| 166 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 167 | /* CLKSEL_CON23 */ |
| 168 | PCLK_PERILP0_DIV_CON_MASK = 0x7, |
| 169 | PCLK_PERILP0_DIV_CON_SHIFT = 12, |
| 170 | HCLK_PERILP0_DIV_CON_MASK = 3, |
| 171 | HCLK_PERILP0_DIV_CON_SHIFT = 8, |
| 172 | ACLK_PERILP0_PLL_SEL_MASK = 1, |
| 173 | ACLK_PERILP0_PLL_SEL_SHIFT = 7, |
| 174 | ACLK_PERILP0_PLL_SEL_CPLL = 0, |
| 175 | ACLK_PERILP0_PLL_SEL_GPLL = 1, |
| 176 | ACLK_PERILP0_DIV_CON_MASK = 0x1f, |
| 177 | ACLK_PERILP0_DIV_CON_SHIFT = 0, |
| 178 | |
| 179 | /* CLKSEL_CON25 */ |
| 180 | PCLK_PERILP1_DIV_CON_MASK = 0x7, |
| 181 | PCLK_PERILP1_DIV_CON_SHIFT = 8, |
| 182 | HCLK_PERILP1_PLL_SEL_MASK = 1, |
| 183 | HCLK_PERILP1_PLL_SEL_SHIFT = 7, |
| 184 | HCLK_PERILP1_PLL_SEL_CPLL = 0, |
| 185 | HCLK_PERILP1_PLL_SEL_GPLL = 1, |
| 186 | HCLK_PERILP1_DIV_CON_MASK = 0x1f, |
| 187 | HCLK_PERILP1_DIV_CON_SHIFT = 0, |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 188 | |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 189 | /* CLKSEL_CON26 */ |
| 190 | CLK_SARADC_DIV_CON_MASK = 0xff, |
| 191 | CLK_SARADC_DIV_CON_SHIFT = 8, |
| 192 | |
Shunqian Zheng | f4181ce | 2016-05-06 16:50:48 +0800 | [diff] [blame] | 193 | /* CLKSEL_CON27 */ |
| 194 | CLK_TSADC_SEL_X24M = 0x0, |
| 195 | CLK_TSADC_SEL_MASK = 1, |
| 196 | CLK_TSADC_SEL_SHIFT = 15, |
| 197 | CLK_TSADC_DIV_CON_MASK = 0x3ff, |
| 198 | CLK_TSADC_DIV_CON_SHIFT = 0, |
| 199 | |
Lin Huang | 4ecccff | 2017-01-18 09:44:34 +0800 | [diff] [blame] | 200 | /* CLKSEL_CON44 */ |
| 201 | CLK_PCLK_EDP_PLL_SEL_MASK = 1, |
| 202 | CLK_PCLK_EDP_PLL_SEL_SHIFT = 15, |
| 203 | CLK_PCLK_EDP_PLL_SEL_CPLL = 0, |
| 204 | CLK_PCLK_EDP_DIV_CON_MASK = 0x3f, |
| 205 | CLK_PCLK_EDP_DIV_CON_SHIFT = 8, |
| 206 | |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 207 | /* CLKSEL_CON47 & CLKSEL_CON48 */ |
| 208 | ACLK_VOP_PLL_SEL_MASK = 0x3, |
| 209 | ACLK_VOP_PLL_SEL_SHIFT = 6, |
| 210 | ACLK_VOP_PLL_SEL_CPLL = 0x1, |
| 211 | ACLK_VOP_DIV_CON_MASK = 0x1f, |
| 212 | ACLK_VOP_DIV_CON_SHIFT = 0, |
| 213 | |
| 214 | /* CLKSEL_CON49 & CLKSEL_CON50 */ |
| 215 | DCLK_VOP_DCLK_SEL_MASK = 1, |
| 216 | DCLK_VOP_DCLK_SEL_SHIFT = 11, |
| 217 | DCLK_VOP_DCLK_SEL_DIVOUT = 0, |
| 218 | DCLK_VOP_PLL_SEL_MASK = 3, |
| 219 | DCLK_VOP_PLL_SEL_SHIFT = 8, |
| 220 | DCLK_VOP_PLL_SEL_VPLL = 0, |
| 221 | DCLK_VOP_DIV_CON_MASK = 0xff, |
| 222 | DCLK_VOP_DIV_CON_SHIFT = 0, |
| 223 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 224 | /* CLKSEL_CON58 */ |
| 225 | CLK_SPI_PLL_SEL_MASK = 1, |
| 226 | CLK_SPI_PLL_SEL_CPLL = 0, |
| 227 | CLK_SPI_PLL_SEL_GPLL = 1, |
| 228 | CLK_SPI_PLL_DIV_CON_MASK = 0x7f, |
| 229 | CLK_SPI5_PLL_DIV_CON_SHIFT = 8, |
| 230 | CLK_SPI5_PLL_SEL_SHIFT = 15, |
| 231 | |
| 232 | /* CLKSEL_CON59 */ |
| 233 | CLK_SPI1_PLL_SEL_SHIFT = 15, |
| 234 | CLK_SPI1_PLL_DIV_CON_SHIFT = 8, |
| 235 | CLK_SPI0_PLL_SEL_SHIFT = 7, |
| 236 | CLK_SPI0_PLL_DIV_CON_SHIFT = 0, |
| 237 | |
| 238 | /* CLKSEL_CON60 */ |
| 239 | CLK_SPI4_PLL_SEL_SHIFT = 15, |
| 240 | CLK_SPI4_PLL_DIV_CON_SHIFT = 8, |
| 241 | CLK_SPI2_PLL_SEL_SHIFT = 7, |
| 242 | CLK_SPI2_PLL_DIV_CON_SHIFT = 0, |
| 243 | |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 244 | /* CLKSEL_CON61 */ |
| 245 | CLK_I2C_PLL_SEL_MASK = 1, |
| 246 | CLK_I2C_PLL_SEL_CPLL = 0, |
| 247 | CLK_I2C_PLL_SEL_GPLL = 1, |
| 248 | CLK_I2C5_PLL_SEL_SHIFT = 15, |
| 249 | CLK_I2C5_DIV_CON_SHIFT = 8, |
| 250 | CLK_I2C1_PLL_SEL_SHIFT = 7, |
| 251 | CLK_I2C1_DIV_CON_SHIFT = 0, |
| 252 | |
| 253 | /* CLKSEL_CON62 */ |
| 254 | CLK_I2C6_PLL_SEL_SHIFT = 15, |
| 255 | CLK_I2C6_DIV_CON_SHIFT = 8, |
| 256 | CLK_I2C2_PLL_SEL_SHIFT = 7, |
| 257 | CLK_I2C2_DIV_CON_SHIFT = 0, |
| 258 | |
| 259 | /* CLKSEL_CON63 */ |
| 260 | CLK_I2C7_PLL_SEL_SHIFT = 15, |
| 261 | CLK_I2C7_DIV_CON_SHIFT = 8, |
| 262 | CLK_I2C3_PLL_SEL_SHIFT = 7, |
| 263 | CLK_I2C3_DIV_CON_SHIFT = 0, |
| 264 | |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 265 | /* CRU_SOFTRST_CON4 */ |
| 266 | RESETN_DDR0_REQ_MASK = 1, |
| 267 | RESETN_DDR0_REQ_SHIFT = 8, |
| 268 | RESETN_DDRPHY0_REQ_MASK = 1, |
| 269 | RESETN_DDRPHY0_REQ_SHIFT = 9, |
| 270 | RESETN_DDR1_REQ_MASK = 1, |
| 271 | RESETN_DDR1_REQ_SHIFT = 12, |
| 272 | RESETN_DDRPHY1_REQ_MASK = 1, |
| 273 | RESETN_DDRPHY1_REQ_SHIFT = 13, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 274 | }; |
| 275 | |
| 276 | #define VCO_MAX_KHZ (3200 * (MHz / KHz)) |
| 277 | #define VCO_MIN_KHZ (800 * (MHz / KHz)) |
| 278 | #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) |
| 279 | #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) |
| 280 | |
| 281 | /* the div restrictions of pll in integer mode, |
| 282 | * these are defined in * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 |
| 283 | */ |
| 284 | #define PLL_DIV_MIN 16 |
| 285 | #define PLL_DIV_MAX 3200 |
| 286 | |
| 287 | /* How to calculate the PLL(from TRM V0.3 Part 1 Page 63): |
| 288 | * Formulas also embedded within the Fractional PLL Verilog model: |
| 289 | * If DSMPD = 1 (DSM is disabled, "integer mode") |
| 290 | * FOUTVCO = FREF / REFDIV * FBDIV |
| 291 | * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 |
| 292 | * Where: |
| 293 | * FOUTVCO = Fractional PLL non-divided output frequency |
| 294 | * FOUTPOSTDIV = Fractional PLL divided output frequency |
| 295 | * (output of second post divider) |
| 296 | * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) |
| 297 | * REFDIV = Fractional PLL input reference clock divider |
| 298 | * FBDIV = Integer value programmed into feedback divide |
| 299 | * |
| 300 | */ |
| 301 | static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) |
| 302 | { |
| 303 | /* All 8 PLLs have same VCO and output frequency range restrictions. */ |
| 304 | u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; |
| 305 | u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; |
| 306 | |
| 307 | printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " |
| 308 | "postdiv2=%d, vco=%u khz, output=%u khz\n", |
| 309 | pll_con, div->fbdiv, div->refdiv, div->postdiv1, |
| 310 | div->postdiv2, vco_khz, output_khz); |
| 311 | assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && |
| 312 | output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && |
| 313 | div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); |
| 314 | |
| 315 | /* When power on or changing PLL setting, |
| 316 | * we must force PLL into slow mode to ensure output stable clock. |
| 317 | */ |
| 318 | write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT, |
| 319 | PLL_MODE_SLOW << PLL_MODE_SHIFT)); |
| 320 | |
| 321 | /* use integer mode */ |
| 322 | write32(&pll_con[3], |
| 323 | RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, |
| 324 | PLL_INTEGER_MODE << PLL_DSMPD_SHIFT)); |
| 325 | |
| 326 | write32(&pll_con[0], RK_CLRSETBITS(PLL_FBDIV_MASK << PLL_FBDIV_SHIFT, |
| 327 | div->fbdiv << PLL_FBDIV_SHIFT)); |
| 328 | write32(&pll_con[1], |
| 329 | RK_CLRSETBITS(PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | |
| 330 | PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | |
| 331 | PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, |
| 332 | (div->postdiv2 << PLL_POSTDIV2_SHIFT) | |
| 333 | (div->postdiv1 << PLL_POSTDIV1_SHIFT) | |
| 334 | (div->refdiv << PLL_REFDIV_SHIFT))); |
| 335 | |
| 336 | /* waiting for pll lock */ |
| 337 | while (!(read32(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) |
| 338 | udelay(1); |
| 339 | |
| 340 | /* pll enter normal mode */ |
| 341 | write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT, |
| 342 | PLL_MODE_NORM << PLL_MODE_SHIFT)); |
| 343 | } |
| 344 | |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 345 | /* |
| 346 | * Configure the DPLL spread spectrum feature on memory clock. |
| 347 | * Configure sequence: |
Martin Roth | 9641a92 | 2018-05-20 17:46:51 -0600 | [diff] [blame] | 348 | * 1. PLL been configured as frac mode, and DACPD should be set to 1'b0. |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 349 | * 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with |
| 350 | * extern wave table). |
Martin Roth | 9641a92 | 2018-05-20 17:46:51 -0600 | [diff] [blame] | 351 | * 3. set ssmod_disable_sscg = 1'b0, and set ssmod_bp = 1'b0. |
| 352 | * 4. Assert RESET = 1'b1 to SSMOD. |
| 353 | * 5. RESET = 1'b0 on SSMOD. |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 354 | * 6. Adjust SPREAD/DIVVAL/DOWNSPREAD. |
| 355 | */ |
| 356 | static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) |
| 357 | { |
| 358 | u32 divval; |
| 359 | |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 360 | assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6); |
| 361 | |
| 362 | /* |
| 363 | * Need to acquire ~30kHZ which is the target modulation frequency. |
| 364 | * The modulation frequency ~ 30kHz= OSC_HZ/revdiv/128/divval |
| 365 | * (the 128 is the number points in the query table). |
| 366 | */ |
| 367 | divval = OSC_HZ / 128 / (30 * KHz) / dpll_cfg->refdiv; |
| 368 | |
| 369 | /* |
| 370 | * Use frac mode. |
| 371 | * Make sure the output frequency isn't offset, set 0 for Fractional |
| 372 | * part of feedback divide. |
| 373 | */ |
| 374 | write32(&cru_ptr->dpll_con[3], |
| 375 | RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, |
| 376 | PLL_FRAC_MODE << PLL_DSMPD_SHIFT)); |
| 377 | clrsetbits_le32(&cru_ptr->dpll_con[2], |
| 378 | PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, |
| 379 | 0 << PLL_FRACDIV_SHIFT); |
| 380 | |
| 381 | /* |
| 382 | * Configure SSC divval. |
| 383 | * Spread amplitude range = 0.1 * SPREAD[4:0] (%). |
| 384 | * The below 8 means SPREAD[4:0] that appears to mitigate EMI on boards |
| 385 | * tested. Center and down spread modulation amplitudes based on the |
| 386 | * value of SPREAD. |
| 387 | * SPREAD[4:0] Center Spread Down Spread |
| 388 | * 0 0 0 |
Martin Roth | 9641a92 | 2018-05-20 17:46:51 -0600 | [diff] [blame] | 389 | * 1 +/-0.1% -0.10% |
| 390 | * 2 +/-0.2% -0.20% |
| 391 | * 3 +/-0.3% -0.30% |
| 392 | * 4 +/-0.4% -0.40% |
| 393 | * 5 +/-0.5% -0.50% |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 394 | * ... |
Martin Roth | 9641a92 | 2018-05-20 17:46:51 -0600 | [diff] [blame] | 395 | * 31 +/-3.1% -3.10% |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 396 | */ |
| 397 | write32(&cru_ptr->dpll_con[4], |
| 398 | RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT, |
| 399 | divval << PLL_SSMOD_DIVVAL_SHIFT)); |
| 400 | write32(&cru_ptr->dpll_con[4], |
| 401 | RK_CLRSETBITS(PLL_SSMOD_SPREADAMP_MASK << |
| 402 | PLL_SSMOD_SPREADAMP_SHIFT, |
| 403 | 8 << PLL_SSMOD_SPREADAMP_SHIFT)); |
| 404 | |
| 405 | /* Enable SSC for DPLL */ |
| 406 | write32(&cru_ptr->dpll_con[4], |
| 407 | RK_CLRBITS(PLL_SSMOD_BP_MASK << PLL_SSMOD_BP_SHIFT | |
| 408 | PLL_SSMOD_DIS_SSCG_MASK << PLL_SSMOD_DIS_SSCG_SHIFT)); |
| 409 | |
| 410 | /* Deassert reset SSMOD */ |
| 411 | write32(&cru_ptr->dpll_con[4], |
| 412 | RK_CLRBITS(PLL_SSMOD_RESET_MASK << PLL_SSMOD_RESET_SHIFT)); |
| 413 | |
| 414 | udelay(20); |
| 415 | } |
| 416 | |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 417 | static int pll_para_config(u32 freq_hz, struct pll_div *div) |
| 418 | { |
| 419 | u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; |
| 420 | u32 postdiv1, postdiv2 = 1; |
| 421 | u32 fref_khz; |
| 422 | u32 diff_khz, best_diff_khz; |
| 423 | const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; |
| 424 | const u32 max_postdiv1 = 7, max_postdiv2 = 7; |
| 425 | u32 vco_khz; |
| 426 | u32 freq_khz = freq_hz / KHz; |
| 427 | |
| 428 | if (!freq_hz) { |
| 429 | printk(BIOS_ERR, "%s: the frequency can't be 0 Hz\n", __func__); |
| 430 | return -1; |
| 431 | } |
| 432 | |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 433 | postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 434 | if (postdiv1 > max_postdiv1) { |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 435 | postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); |
| 436 | postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | vco_khz = freq_khz * postdiv1 * postdiv2; |
| 440 | |
| 441 | if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || |
| 442 | postdiv2 > max_postdiv2) { |
| 443 | printk(BIOS_ERR, "%s: Cannot find out a supported VCO" |
| 444 | " for Frequency (%uHz).\n", __func__, freq_hz); |
| 445 | return -1; |
| 446 | } |
| 447 | |
| 448 | div->postdiv1 = postdiv1; |
| 449 | div->postdiv2 = postdiv2; |
| 450 | |
| 451 | best_diff_khz = vco_khz; |
| 452 | for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { |
| 453 | fref_khz = ref_khz / refdiv; |
| 454 | |
| 455 | fbdiv = vco_khz / fref_khz; |
| 456 | if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) |
| 457 | continue; |
| 458 | diff_khz = vco_khz - fbdiv * fref_khz; |
| 459 | if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { |
| 460 | fbdiv++; |
| 461 | diff_khz = fref_khz - diff_khz; |
| 462 | } |
| 463 | |
| 464 | if (diff_khz >= best_diff_khz) |
| 465 | continue; |
| 466 | |
| 467 | best_diff_khz = diff_khz; |
| 468 | div->refdiv = refdiv; |
| 469 | div->fbdiv = fbdiv; |
| 470 | } |
| 471 | |
| 472 | if (best_diff_khz > 4 * (MHz/KHz)) { |
| 473 | printk(BIOS_ERR, "%s: Failed to match output frequency %u, " |
| 474 | "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, |
| 475 | best_diff_khz * KHz); |
| 476 | return -1; |
| 477 | } |
| 478 | return 0; |
| 479 | } |
| 480 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 481 | void rkclk_init(void) |
| 482 | { |
| 483 | u32 aclk_div; |
| 484 | u32 hclk_div; |
| 485 | u32 pclk_div; |
| 486 | |
| 487 | /* some cru registers changed by bootrom, we'd better reset them to |
| 488 | * reset/default values described in TRM to avoid confusion in kernel. |
| 489 | * Please consider these threee lines as a fix of bootrom bug. |
| 490 | */ |
| 491 | write32(&cru_ptr->clksel_con[12], 0xffff4101); |
| 492 | write32(&cru_ptr->clksel_con[19], 0xffff033f); |
| 493 | write32(&cru_ptr->clksel_con[56], 0x00030003); |
| 494 | |
| 495 | /* configure pmu pll(ppll) */ |
| 496 | rkclk_set_pll(&pmucru_ptr->ppll_con[0], &ppll_init_cfg); |
| 497 | |
| 498 | /* configure pmu pclk */ |
| 499 | pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 500 | assert((unsigned int)(PPLL_HZ - (pclk_div + 1) * PMU_PCLK_HZ) <= pclk_div |
| 501 | && pclk_div <= 0x1f); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 502 | write32(&pmucru_ptr->pmucru_clksel[0], |
| 503 | RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT, |
| 504 | pclk_div << PMU_PCLK_DIV_CON_SHIFT)); |
| 505 | |
| 506 | /* configure gpll cpll */ |
| 507 | rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg); |
| 508 | rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg); |
| 509 | |
| 510 | /* configure perihp aclk, hclk, pclk */ |
| 511 | aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 512 | assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 513 | |
| 514 | hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; |
| 515 | assert((hclk_div + 1) * PERIHP_HCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 516 | PERIHP_ACLK_HZ && (hclk_div <= 0x3)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 517 | |
| 518 | pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; |
| 519 | assert((pclk_div + 1) * PERIHP_PCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 520 | PERIHP_ACLK_HZ && (pclk_div <= 0x7)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 521 | |
| 522 | write32(&cru_ptr->clksel_con[14], |
| 523 | RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK << |
| 524 | PCLK_PERIHP_DIV_CON_SHIFT | |
| 525 | HCLK_PERIHP_DIV_CON_MASK << |
| 526 | HCLK_PERIHP_DIV_CON_SHIFT | |
| 527 | ACLK_PERIHP_PLL_SEL_MASK << |
| 528 | ACLK_PERIHP_PLL_SEL_SHIFT | |
| 529 | ACLK_PERIHP_DIV_CON_MASK << |
| 530 | ACLK_PERIHP_DIV_CON_SHIFT, |
| 531 | pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | |
| 532 | hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | |
| 533 | ACLK_PERIHP_PLL_SEL_GPLL << |
| 534 | ACLK_PERIHP_PLL_SEL_SHIFT | |
| 535 | aclk_div << ACLK_PERIHP_DIV_CON_SHIFT)); |
| 536 | |
| 537 | /* configure perilp0 aclk, hclk, pclk */ |
| 538 | aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 539 | assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 540 | |
| 541 | hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; |
| 542 | assert((hclk_div + 1) * PERILP0_HCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 543 | PERILP0_ACLK_HZ && (hclk_div <= 0x3)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 544 | |
| 545 | pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; |
| 546 | assert((pclk_div + 1) * PERILP0_PCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 547 | PERILP0_ACLK_HZ && (pclk_div <= 0x7)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 548 | |
| 549 | write32(&cru_ptr->clksel_con[23], |
| 550 | RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK << |
| 551 | PCLK_PERILP0_DIV_CON_SHIFT | |
| 552 | HCLK_PERILP0_DIV_CON_MASK << |
| 553 | HCLK_PERILP0_DIV_CON_SHIFT | |
| 554 | ACLK_PERILP0_PLL_SEL_MASK << |
| 555 | ACLK_PERILP0_PLL_SEL_SHIFT | |
| 556 | ACLK_PERILP0_DIV_CON_MASK << |
| 557 | ACLK_PERILP0_DIV_CON_SHIFT, |
| 558 | pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | |
| 559 | hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | |
| 560 | ACLK_PERILP0_PLL_SEL_GPLL << |
| 561 | ACLK_PERILP0_PLL_SEL_SHIFT | |
| 562 | aclk_div << ACLK_PERILP0_DIV_CON_SHIFT)); |
| 563 | |
| 564 | /* perilp1 hclk select gpll as source */ |
| 565 | hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; |
| 566 | assert((hclk_div + 1) * PERILP1_HCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 567 | GPLL_HZ && (hclk_div <= 0x1f)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 568 | |
Julius Werner | f7d519c | 2016-09-02 23:48:10 -0700 | [diff] [blame] | 569 | pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; |
| 570 | assert((pclk_div + 1) * PERILP1_PCLK_HZ == |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 571 | PERILP1_HCLK_HZ && (pclk_div <= 0x7)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 572 | |
| 573 | write32(&cru_ptr->clksel_con[25], |
| 574 | RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << |
| 575 | PCLK_PERILP1_DIV_CON_SHIFT | |
| 576 | HCLK_PERILP1_DIV_CON_MASK << |
| 577 | HCLK_PERILP1_DIV_CON_SHIFT | |
| 578 | HCLK_PERILP1_PLL_SEL_MASK << |
| 579 | HCLK_PERILP1_PLL_SEL_SHIFT, |
| 580 | pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | |
| 581 | hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | |
| 582 | HCLK_PERILP1_PLL_SEL_GPLL << |
| 583 | HCLK_PERILP1_PLL_SEL_SHIFT)); |
| 584 | } |
| 585 | |
Julius Werner | 7f96589 | 2016-08-29 15:07:58 -0700 | [diff] [blame] | 586 | void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster) |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 587 | { |
Julius Werner | 7f96589 | 2016-08-29 15:07:58 -0700 | [diff] [blame] | 588 | u32 aclkm_div, atclk_div, pclk_dbg_div, apll_hz; |
| 589 | int con_base, parent; |
| 590 | u32 *pll_con; |
Lin Huang | e3d78b8 | 2016-06-28 11:10:54 +0800 | [diff] [blame] | 591 | |
Julius Werner | 7f96589 | 2016-08-29 15:07:58 -0700 | [diff] [blame] | 592 | switch (cluster) { |
| 593 | case CPU_CLUSTER_LITTLE: |
| 594 | con_base = 0; |
| 595 | parent = CLK_CORE_PLL_SEL_ALPLL; |
| 596 | pll_con = &cru_ptr->apll_l_con[0]; |
| 597 | break; |
| 598 | case CPU_CLUSTER_BIG: |
| 599 | default: |
| 600 | con_base = 2; |
| 601 | parent = CLK_CORE_PLL_SEL_ABPLL; |
| 602 | pll_con = &cru_ptr->apll_b_con[0]; |
| 603 | break; |
| 604 | } |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 605 | |
Julius Werner | 7f96589 | 2016-08-29 15:07:58 -0700 | [diff] [blame] | 606 | apll_hz = apll_cfgs[freq]->freq; |
| 607 | rkclk_set_pll(pll_con, apll_cfgs[freq]); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 608 | |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 609 | aclkm_div = DIV_ROUND_UP(apll_hz, ACLKM_CORE_HZ) - 1; |
| 610 | pclk_dbg_div = DIV_ROUND_UP(apll_hz, PCLK_DBG_HZ) - 1; |
| 611 | atclk_div = DIV_ROUND_UP(apll_hz, ATCLK_CORE_HZ) - 1; |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 612 | |
Lin Huang | bdd06de | 2016-06-28 15:21:20 +0800 | [diff] [blame] | 613 | write32(&cru_ptr->clksel_con[con_base], |
| 614 | RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK << |
| 615 | ACLKM_CORE_DIV_CON_SHIFT | |
| 616 | CLK_CORE_PLL_SEL_MASK << CLK_CORE_PLL_SEL_SHIFT | |
| 617 | CLK_CORE_DIV_MASK << CLK_CORE_DIV_SHIFT, |
| 618 | aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | |
| 619 | parent << CLK_CORE_PLL_SEL_SHIFT | |
| 620 | 0 << CLK_CORE_DIV_SHIFT)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 621 | |
Lin Huang | bdd06de | 2016-06-28 15:21:20 +0800 | [diff] [blame] | 622 | write32(&cru_ptr->clksel_con[con_base + 1], |
| 623 | RK_CLRSETBITS(PCLK_DBG_DIV_MASK << PCLK_DBG_DIV_SHIFT | |
| 624 | ATCLK_CORE_DIV_MASK << ATCLK_CORE_DIV_SHIFT, |
| 625 | pclk_dbg_div << PCLK_DBG_DIV_SHIFT | |
| 626 | atclk_div << ATCLK_CORE_DIV_SHIFT)); |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 627 | } |
Lin Huang | f5702e7 | 2016-03-19 22:45:19 +0800 | [diff] [blame] | 628 | |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 629 | void rkclk_configure_ddr(unsigned int hz) |
| 630 | { |
| 631 | struct pll_div dpll_cfg; |
| 632 | |
| 633 | /* IC ECO bug, need to set this register */ |
| 634 | write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xc000c000); |
| 635 | |
| 636 | /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ |
| 637 | switch (hz) { |
| 638 | case 200*MHz: |
| 639 | dpll_cfg = (struct pll_div) |
Caesar Wang | a0199d8 | 2017-06-22 16:14:58 +0800 | [diff] [blame] | 640 | {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}; |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 641 | break; |
| 642 | case 300*MHz: |
| 643 | dpll_cfg = (struct pll_div) |
| 644 | {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; |
| 645 | break; |
| 646 | case 666*MHz: |
| 647 | dpll_cfg = (struct pll_div) |
| 648 | {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; |
| 649 | break; |
| 650 | case 800*MHz: |
| 651 | dpll_cfg = (struct pll_div) |
| 652 | {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; |
| 653 | break; |
Lin Huang | ba2b63a | 2016-07-25 10:06:09 +0800 | [diff] [blame] | 654 | case 933*MHz: |
Shunqian Zheng | 0d9839b | 2016-05-11 15:18:17 +0800 | [diff] [blame] | 655 | dpll_cfg = (struct pll_div) |
Derek Basehore | 8e1a995 | 2016-10-27 13:51:49 -0700 | [diff] [blame] | 656 | {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; |
Shunqian Zheng | 0d9839b | 2016-05-11 15:18:17 +0800 | [diff] [blame] | 657 | break; |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 658 | default: |
| 659 | die("Unsupported SDRAM frequency, add to clock.c!"); |
| 660 | } |
| 661 | rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg); |
Caesar Wang | e085a8a | 2017-05-04 09:24:23 +0800 | [diff] [blame] | 662 | |
| 663 | if (IS_ENABLED(CONFIG_RK3399_SPREAD_SPECTRUM_DDR)) |
| 664 | rkclk_set_dpllssc(&dpll_cfg); |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 665 | } |
| 666 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 667 | #define SPI_CLK_REG_VALUE(bus, clk_div) \ |
| 668 | RK_CLRSETBITS(CLK_SPI_PLL_SEL_MASK << \ |
| 669 | CLK_SPI ##bus## _PLL_SEL_SHIFT | \ |
| 670 | CLK_SPI_PLL_DIV_CON_MASK << \ |
| 671 | CLK_SPI ##bus## _PLL_DIV_CON_SHIFT, \ |
| 672 | CLK_SPI_PLL_SEL_GPLL << \ |
| 673 | CLK_SPI ##bus## _PLL_SEL_SHIFT | \ |
| 674 | (clk_div - 1) << \ |
| 675 | CLK_SPI ##bus## _PLL_DIV_CON_SHIFT) |
| 676 | |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 677 | void rkclk_configure_spi(unsigned int bus, unsigned int hz) |
| 678 | { |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 679 | int src_clk_div; |
| 680 | int pll; |
| 681 | |
| 682 | /* spi3 src clock from ppll, while spi0,1,2,4,5 src clock from gpll */ |
| 683 | pll = (bus == 3) ? PPLL_HZ : GPLL_HZ; |
| 684 | src_clk_div = pll / hz; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 685 | assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll)); |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 686 | |
| 687 | switch (bus) { |
| 688 | case 0: |
| 689 | write32(&cru_ptr->clksel_con[59], |
| 690 | SPI_CLK_REG_VALUE(0, src_clk_div)); |
| 691 | break; |
| 692 | case 1: |
| 693 | write32(&cru_ptr->clksel_con[59], |
| 694 | SPI_CLK_REG_VALUE(1, src_clk_div)); |
| 695 | break; |
| 696 | case 2: |
| 697 | write32(&cru_ptr->clksel_con[60], |
| 698 | SPI_CLK_REG_VALUE(2, src_clk_div)); |
| 699 | break; |
| 700 | case 3: |
| 701 | write32(&pmucru_ptr->pmucru_clksel[1], |
| 702 | RK_CLRSETBITS(SPI3_PLL_SEL_MASK << SPI3_PLL_SEL_SHIFT | |
| 703 | SPI3_DIV_CON_MASK << SPI3_DIV_CON_SHIFT, |
| 704 | SPI3_PLL_SEL_PPLL << SPI3_PLL_SEL_SHIFT | |
| 705 | (src_clk_div - 1) << SPI3_DIV_CON_SHIFT)); |
| 706 | break; |
| 707 | case 4: |
| 708 | write32(&cru_ptr->clksel_con[60], |
| 709 | SPI_CLK_REG_VALUE(4, src_clk_div)); |
| 710 | break; |
| 711 | case 5: |
| 712 | write32(&cru_ptr->clksel_con[58], |
| 713 | SPI_CLK_REG_VALUE(5, src_clk_div)); |
| 714 | break; |
| 715 | default: |
| 716 | printk(BIOS_ERR, "do not support this spi bus\n"); |
| 717 | } |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 718 | } |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 719 | |
| 720 | #define I2C_CLK_REG_VALUE(bus, clk_div) \ |
| 721 | RK_CLRSETBITS(I2C_DIV_CON_MASK << \ |
| 722 | CLK_I2C ##bus## _DIV_CON_SHIFT | \ |
| 723 | CLK_I2C_PLL_SEL_MASK << \ |
| 724 | CLK_I2C ##bus## _PLL_SEL_SHIFT, \ |
| 725 | (clk_div - 1) << \ |
| 726 | CLK_I2C ##bus## _DIV_CON_SHIFT | \ |
| 727 | CLK_I2C_PLL_SEL_GPLL << \ |
| 728 | CLK_I2C ##bus## _PLL_SEL_SHIFT) |
| 729 | #define PMU_I2C_CLK_REG_VALUE(bus, clk_div) \ |
| 730 | RK_CLRSETBITS(I2C_DIV_CON_MASK << I2C ##bus## _DIV_CON_SHIFT, \ |
| 731 | (clk_div - 1) << I2C ##bus## _DIV_CON_SHIFT) |
| 732 | |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 733 | uint32_t rkclk_i2c_clock_for_bus(unsigned int bus) |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 734 | { |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 735 | int src_clk_div, pll, freq; |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 736 | |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 737 | /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll */ |
| 738 | if (bus == 0 || bus == 4 || bus == 8) { |
| 739 | pll = PPLL_HZ; |
| 740 | freq = 338*MHz; |
| 741 | } else { |
| 742 | pll = GPLL_HZ; |
| 743 | freq = 198*MHz; |
| 744 | } |
| 745 | src_clk_div = pll / freq; |
| 746 | assert((src_clk_div - 1 <= 127) && (src_clk_div * freq == pll)); |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 747 | |
| 748 | switch (bus) { |
| 749 | case 0: |
| 750 | write32(&pmucru_ptr->pmucru_clksel[2], |
| 751 | PMU_I2C_CLK_REG_VALUE(0, src_clk_div)); |
| 752 | break; |
| 753 | case 1: |
| 754 | write32(&cru_ptr->clksel_con[61], |
| 755 | I2C_CLK_REG_VALUE(1, src_clk_div)); |
| 756 | break; |
| 757 | case 2: |
| 758 | write32(&cru_ptr->clksel_con[62], |
| 759 | I2C_CLK_REG_VALUE(2, src_clk_div)); |
| 760 | break; |
| 761 | case 3: |
| 762 | write32(&cru_ptr->clksel_con[63], |
| 763 | I2C_CLK_REG_VALUE(3, src_clk_div)); |
| 764 | break; |
| 765 | case 4: |
| 766 | write32(&pmucru_ptr->pmucru_clksel[3], |
| 767 | PMU_I2C_CLK_REG_VALUE(4, src_clk_div)); |
| 768 | break; |
| 769 | case 5: |
| 770 | write32(&cru_ptr->clksel_con[61], |
| 771 | I2C_CLK_REG_VALUE(5, src_clk_div)); |
| 772 | break; |
| 773 | case 6: |
| 774 | write32(&cru_ptr->clksel_con[62], |
| 775 | I2C_CLK_REG_VALUE(6, src_clk_div)); |
| 776 | break; |
| 777 | case 7: |
| 778 | write32(&cru_ptr->clksel_con[63], |
| 779 | I2C_CLK_REG_VALUE(7, src_clk_div)); |
| 780 | break; |
| 781 | case 8: |
| 782 | write32(&pmucru_ptr->pmucru_clksel[2], |
| 783 | PMU_I2C_CLK_REG_VALUE(8, src_clk_div)); |
| 784 | break; |
| 785 | default: |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 786 | die("unknown i2c bus\n"); |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 787 | } |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 788 | |
| 789 | return freq; |
| 790 | } |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 791 | |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 792 | static u32 clk_gcd(u32 a, u32 b) |
| 793 | { |
| 794 | while (b != 0) { |
| 795 | int r = b; |
| 796 | b = a % b; |
| 797 | a = r; |
| 798 | } |
| 799 | return a; |
| 800 | } |
| 801 | |
| 802 | void rkclk_configure_i2s(unsigned int hz) |
| 803 | { |
| 804 | int n, d; |
| 805 | int v; |
| 806 | |
| 807 | /** |
Elyes HAOUAS | 809aeee | 2018-08-07 12:14:33 +0200 | [diff] [blame] | 808 | * clk_i2s0_sel: divider output from fraction |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 809 | * clk_i2s0_pll_sel source clock: cpll |
| 810 | * clk_i2s0_div_con: 1 (div+1) |
| 811 | */ |
| 812 | write32(&cru_ptr->clksel_con[28], |
| 813 | RK_CLRSETBITS(3 << 8 | 1 << 7 | 0x7f << 0, |
| 814 | 1 << 8 | 0 << 7 | 0 << 0)); |
| 815 | |
| 816 | /* make sure and enable i2s0 path gates */ |
| 817 | write32(&cru_ptr->clkgate_con[8], |
| 818 | RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3)); |
| 819 | |
| 820 | /* set frac divider */ |
| 821 | v = clk_gcd(CPLL_HZ, hz); |
| 822 | n = (CPLL_HZ / v) & (0xffff); |
| 823 | d = (hz / v) & (0xffff); |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 824 | assert(hz == (u64)CPLL_HZ * d / n); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 825 | write32(&cru_ptr->clksel_con[96], d << 16 | n); |
| 826 | |
| 827 | /** |
| 828 | * clk_i2sout_sel clk_i2s |
| 829 | * clk_i2s_ch_sel: clk_i2s0 |
| 830 | */ |
| 831 | write32(&cru_ptr->clksel_con[31], |
| 832 | RK_CLRSETBITS(1 << 2 | 3 << 0, |
| 833 | 0 << 2 | 0 << 0)); |
| 834 | } |
| 835 | |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 836 | void rkclk_configure_saradc(unsigned int hz) |
| 837 | { |
| 838 | int src_clk_div; |
| 839 | |
| 840 | /* saradc src clk from 24MHz */ |
| 841 | src_clk_div = 24 * MHz / hz; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 842 | assert((src_clk_div - 1 <= 255) && (src_clk_div * hz == 24 * MHz)); |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 843 | |
| 844 | write32(&cru_ptr->clksel_con[26], |
| 845 | RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK << |
| 846 | CLK_SARADC_DIV_CON_SHIFT, |
| 847 | (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT)); |
| 848 | } |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 849 | |
| 850 | void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) |
| 851 | { |
| 852 | u32 div; |
| 853 | void *reg_addr = vop_id ? &cru_ptr->clksel_con[48] : |
| 854 | &cru_ptr->clksel_con[47]; |
| 855 | |
| 856 | /* vop aclk source clk: cpll */ |
| 857 | div = CPLL_HZ / aclk_hz; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 858 | assert((div - 1 <= 31) && (div * aclk_hz == CPLL_HZ)); |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 859 | |
| 860 | write32(reg_addr, RK_CLRSETBITS( |
| 861 | ACLK_VOP_PLL_SEL_MASK << ACLK_VOP_PLL_SEL_SHIFT | |
| 862 | ACLK_VOP_DIV_CON_MASK << ACLK_VOP_DIV_CON_SHIFT, |
| 863 | ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | |
| 864 | (div - 1) << ACLK_VOP_DIV_CON_SHIFT)); |
| 865 | } |
| 866 | |
| 867 | int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) |
| 868 | { |
| 869 | struct pll_div vpll_config = {0}; |
| 870 | void *reg_addr = vop_id ? &cru_ptr->clksel_con[50] : |
| 871 | &cru_ptr->clksel_con[49]; |
| 872 | |
| 873 | /* vop dclk source from vpll, and equals to vpll(means div == 1) */ |
| 874 | if (pll_para_config(dclk_hz, &vpll_config)) |
| 875 | return -1; |
| 876 | |
| 877 | rkclk_set_pll(&cru_ptr->vpll_con[0], &vpll_config); |
| 878 | |
| 879 | write32(reg_addr, RK_CLRSETBITS( |
| 880 | DCLK_VOP_DCLK_SEL_MASK << DCLK_VOP_DCLK_SEL_SHIFT | |
| 881 | DCLK_VOP_PLL_SEL_MASK << DCLK_VOP_PLL_SEL_SHIFT | |
| 882 | DCLK_VOP_DIV_CON_MASK << DCLK_VOP_DIV_CON_SHIFT, |
| 883 | DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | |
| 884 | DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | |
| 885 | (1 - 1) << DCLK_VOP_DIV_CON_SHIFT)); |
| 886 | |
| 887 | return 0; |
| 888 | } |
Shunqian Zheng | f4181ce | 2016-05-06 16:50:48 +0800 | [diff] [blame] | 889 | |
| 890 | void rkclk_configure_tsadc(unsigned int hz) |
| 891 | { |
| 892 | int src_clk_div; |
| 893 | |
| 894 | /* use 24M as src clock */ |
| 895 | src_clk_div = OSC_HZ / hz; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 896 | assert((src_clk_div - 1 <= 1023) && (src_clk_div * hz == OSC_HZ)); |
Shunqian Zheng | f4181ce | 2016-05-06 16:50:48 +0800 | [diff] [blame] | 897 | |
| 898 | write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS( |
| 899 | CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT | |
| 900 | CLK_TSADC_SEL_MASK << CLK_TSADC_SEL_SHIFT, |
| 901 | src_clk_div << CLK_TSADC_DIV_CON_SHIFT | |
| 902 | CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT)); |
| 903 | } |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 904 | |
| 905 | void rkclk_configure_emmc(void) |
| 906 | { |
| 907 | int src_clk_div; |
Ziyuan Xu | c53cf64 | 2016-09-18 10:49:52 +0800 | [diff] [blame] | 908 | int aclk_emmc = 148500*KHz; |
| 909 | int clk_emmc = 148500*KHz; |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 910 | |
| 911 | /* Select aclk_emmc source from GPLL */ |
| 912 | src_clk_div = GPLL_HZ / aclk_emmc; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 913 | assert((src_clk_div - 1 <= 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 914 | |
| 915 | write32(&cru_ptr->clksel_con[21], |
| 916 | RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK << |
| 917 | ACLK_EMMC_PLL_SEL_SHIFT | |
| 918 | ACLK_EMMC_DIV_CON_MASK << ACLK_EMMC_DIV_CON_SHIFT, |
| 919 | ACLK_EMMC_PLL_SEL_GPLL << |
| 920 | ACLK_EMMC_PLL_SEL_SHIFT | |
| 921 | (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT)); |
| 922 | |
| 923 | /* Select clk_emmc source from GPLL too */ |
| 924 | src_clk_div = GPLL_HZ / clk_emmc; |
Julius Werner | b37c8c0 | 2016-09-06 14:09:16 -0700 | [diff] [blame] | 925 | assert((src_clk_div - 1 <= 127) && (src_clk_div * clk_emmc == GPLL_HZ)); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 926 | |
| 927 | write32(&cru_ptr->clksel_con[22], |
| 928 | RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT | |
| 929 | CLK_EMMC_DIV_CON_MASK << CLK_EMMC_DIV_CON_SHIFT, |
| 930 | CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | |
| 931 | (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT)); |
| 932 | } |
Julius Werner | b6bf1dd | 2016-08-24 19:38:05 -0700 | [diff] [blame] | 933 | |
| 934 | int rkclk_was_watchdog_reset(void) |
| 935 | { |
| 936 | /* Bits 5 and 4 are "second" and "first" global watchdog reset. */ |
| 937 | return read32(&cru_ptr->glb_rst_st) & 0x30; |
| 938 | } |
Lin Huang | 4ecccff | 2017-01-18 09:44:34 +0800 | [diff] [blame] | 939 | |
| 940 | void rkclk_configure_edp(unsigned int hz) |
| 941 | { |
| 942 | int src_clk_div; |
| 943 | |
| 944 | src_clk_div = CPLL_HZ / hz; |
| 945 | assert((src_clk_div - 1 <= 63) && (src_clk_div * hz == CPLL_HZ)); |
| 946 | |
| 947 | write32(&cru_ptr->clksel_con[44], |
| 948 | RK_CLRSETBITS(CLK_PCLK_EDP_PLL_SEL_MASK << |
| 949 | CLK_PCLK_EDP_PLL_SEL_SHIFT | |
| 950 | CLK_PCLK_EDP_DIV_CON_MASK << |
| 951 | CLK_PCLK_EDP_DIV_CON_SHIFT, |
| 952 | CLK_PCLK_EDP_PLL_SEL_CPLL << |
| 953 | CLK_PCLK_EDP_PLL_SEL_SHIFT | |
| 954 | (src_clk_div - 1) << |
| 955 | CLK_PCLK_EDP_DIV_CON_SHIFT)); |
| 956 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 957 | |
| 958 | void rkclk_configure_mipi(void) |
| 959 | { |
| 960 | /* Enable clk_mipidphy_ref and clk_mipidphy_cfg */ |
| 961 | write32(&cru_ptr->clkgate_con[11], |
| 962 | RK_CLRBITS(1 << 14 | 1 << 15)); |
| 963 | /* Enable pclk_mipi_dsi0 */ |
| 964 | write32(&cru_ptr->clkgate_con[29], |
| 965 | RK_CLRBITS(1 << 1)); |
| 966 | } |