Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 6 | * Copyright (C) 2015 Intel Corp. |
Frans Hendriks | bd5233e | 2018-12-05 15:24:48 +0100 | [diff] [blame] | 7 | * Copyright (C) 2018 Eltan B.V. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | */ |
| 18 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 19 | #include <arch/io.h> |
| 20 | #include <arch/acpi.h> |
Lee Leahy | 2bc9cee | 2015-06-30 15:25:44 -0700 | [diff] [blame] | 21 | #include <arch/acpigen.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | #include <bootstate.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 23 | #include "chip.h" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 24 | #include <console/console.h> |
| 25 | #include <cpu/x86/smm.h> |
| 26 | #include <device/device.h> |
| 27 | #include <device/pci.h> |
| 28 | #include <device/pci_ids.h> |
Frans Hendriks | bd5233e | 2018-12-05 15:24:48 +0100 | [diff] [blame] | 29 | #include <pc80/i8254.h> |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame^] | 30 | #include <pc80/i8259.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 31 | #include <romstage_handoff.h> |
Lee Leahy | 2bc9cee | 2015-06-30 15:25:44 -0700 | [diff] [blame] | 32 | #include <soc/acpi.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | #include <soc/iomap.h> |
| 34 | #include <soc/irq.h> |
| 35 | #include <soc/lpc.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 36 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 37 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 38 | #include <soc/ramstage.h> |
| 39 | #include <soc/spi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 40 | #include <spi-generic.h> |
| 41 | #include <stdint.h> |
Hannah Williams | 3fa80a9 | 2017-03-22 16:33:36 -0700 | [diff] [blame] | 42 | #include <reg_script.h> |
| 43 | |
| 44 | static const struct reg_script ops[] = { |
| 45 | REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT, |
| 46 | ~SCNT_MODE, 0), /* put LPC SERIRQ in Quiet Mode */ |
| 47 | REG_SCRIPT_END |
| 48 | }; |
| 49 | |
| 50 | static void enable_serirq_quiet_mode(void) |
| 51 | { |
| 52 | reg_script_run(ops); |
| 53 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 54 | |
| 55 | static inline void |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 56 | add_mmio_resource(struct device *dev, int i, unsigned long addr, |
| 57 | unsigned long size) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 58 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 59 | printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 60 | __FILE__, __func__, dev_name(dev), addr, size); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 61 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 62 | } |
| 63 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 64 | static void sc_add_mmio_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 65 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 66 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 67 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 68 | add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 69 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 70 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 71 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 72 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 73 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 74 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 75 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
| 76 | } |
| 77 | |
| 78 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 79 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 80 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 81 | |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame^] | 82 | /* |
| 83 | * Write PCI config space IRQ assignments. PCI devices have the INT_LINE |
| 84 | * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing |
| 85 | * information to operating systems and drivers. The INT_PIN register is |
| 86 | * generally read only and reports which interrupt pin A - D it uses. The |
| 87 | * INT_LINE register is configurable and reports which IRQ (generally the |
| 88 | * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling |
| 89 | * on devices that are downstream on a PCI bridge into account. |
| 90 | * |
| 91 | * This function will loop through all enabled PCI devices and program the |
| 92 | * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it |
| 93 | * uses. It then configures each interrupt in the pic to be level triggered. |
| 94 | */ |
| 95 | static void write_pci_config_irqs(void) |
| 96 | { |
| 97 | struct device *irq_dev; |
| 98 | struct device *targ_dev; |
| 99 | uint8_t int_line = 0; |
| 100 | uint8_t original_int_pin = 0; |
| 101 | uint8_t new_int_pin = 0; |
| 102 | uint16_t current_bdf = 0; |
| 103 | uint16_t parent_bdf = 0; |
| 104 | uint8_t pirq = 0; |
| 105 | uint8_t device_num = 0; |
| 106 | const struct soc_irq_route *ir = &global_soc_irq_route; |
| 107 | |
| 108 | if (ir == NULL) { |
| 109 | printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments" |
| 110 | " because 'global_braswell_irq_route' structure does" |
| 111 | " not exist\n"); |
| 112 | return; |
| 113 | } |
| 114 | |
| 115 | /* |
| 116 | * Loop through all enabled devices and program their |
| 117 | * INT_LINE, INT_PIN registers from values taken from |
| 118 | * the Interrupt Route registers in the ILB |
| 119 | */ |
| 120 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PIRQ assignments\n"); |
| 121 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 122 | |
| 123 | if ((irq_dev->path.type != DEVICE_PATH_PCI) || |
| 124 | (!irq_dev->enabled)) |
| 125 | continue; |
| 126 | |
| 127 | current_bdf = irq_dev->path.pci.devfn | |
| 128 | irq_dev->bus->secondary << 8; |
| 129 | |
| 130 | /* |
| 131 | * Step 1: Get the INT_PIN and device structure to look for |
| 132 | * in the pirq_data table defined in the mainboard directory. |
| 133 | */ |
| 134 | targ_dev = NULL; |
| 135 | new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); |
| 136 | if (targ_dev == NULL || new_int_pin < 1) |
| 137 | continue; |
| 138 | |
| 139 | /* Get the original INT_PIN for record keeping */ |
| 140 | original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 141 | |
| 142 | parent_bdf = targ_dev->path.pci.devfn |
| 143 | | targ_dev->bus->secondary << 8; |
| 144 | device_num = PCI_SLOT(parent_bdf); |
| 145 | |
| 146 | if (ir->pcidev[device_num] == 0) { |
| 147 | printk(BIOS_WARNING, |
| 148 | "Warning: PCI Device %d does not have an IRQ " |
| 149 | "entry, skipping it\n", device_num); |
| 150 | continue; |
| 151 | } |
| 152 | |
| 153 | /* Find the PIRQ that is attached to the INT_PIN */ |
| 154 | pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) |
| 155 | & 0x7; |
| 156 | |
| 157 | /* Get the INT_LINE this device/function will use */ |
| 158 | int_line = ir->pic[pirq]; |
| 159 | |
| 160 | if (int_line != PIRQ_PIC_IRQDISABLE) { |
| 161 | /* Set this IRQ to level triggered */ |
| 162 | i8259_configure_irq_trigger(int_line, |
| 163 | IRQ_LEVEL_TRIGGERED); |
| 164 | /* Set the Interrupt Line register */ |
| 165 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, |
| 166 | int_line); |
| 167 | } else { |
| 168 | /* |
| 169 | * Set the Interrupt line register as 'unknown' or |
| 170 | * 'unused' |
| 171 | */ |
| 172 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, |
| 173 | PIRQ_PIC_UNKNOWN_UNUSED); |
| 174 | } |
| 175 | |
| 176 | printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", |
| 177 | original_int_pin, pin_to_str(original_int_pin)); |
| 178 | if (parent_bdf != current_bdf) |
| 179 | printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", |
| 180 | new_int_pin, pin_to_str(new_int_pin)); |
| 181 | printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" |
| 182 | "\tINT_LINE\t: 0x%X (IRQ %d)\n", |
| 183 | 'A' + pirq, int_line, int_line); |
| 184 | } |
| 185 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PIRQ assignments\n"); |
| 186 | } |
| 187 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 188 | static inline int io_range_in_default(int base, int size) |
| 189 | { |
| 190 | /* Does it start above the range? */ |
| 191 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 192 | return 0; |
| 193 | |
| 194 | /* Is it entirely contained? */ |
| 195 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 196 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 197 | return 1; |
| 198 | |
| 199 | /* This will return not in range for partial overlaps. */ |
| 200 | return 0; |
| 201 | } |
| 202 | |
| 203 | /* |
| 204 | * Note: this function assumes there is no overlap with the default LPC device's |
| 205 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 206 | */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 207 | static void sc_add_io_resource(struct device *dev, int base, int size, |
| 208 | int index) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 209 | { |
| 210 | struct resource *res; |
| 211 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 212 | printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x, 0x%08x)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 213 | __FILE__, __func__, dev_name(dev), base, size, index); |
| 214 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 215 | if (io_range_in_default(base, size)) |
| 216 | return; |
| 217 | |
| 218 | res = new_resource(dev, index); |
| 219 | res->base = base; |
| 220 | res->size = size; |
| 221 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 222 | } |
| 223 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 224 | static void sc_add_io_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 225 | { |
| 226 | struct resource *res; |
| 227 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 228 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 229 | __FILE__, __func__, dev_name(dev)); |
| 230 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 231 | /* Add the default claimed IO range for the LPC device. */ |
| 232 | res = new_resource(dev, 0); |
| 233 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 234 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 235 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 236 | |
| 237 | /* GPIO */ |
Frans Hendriks | 4b2c12f | 2018-11-22 07:52:38 +0100 | [diff] [blame] | 238 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 239 | |
| 240 | /* ACPI */ |
Frans Hendriks | 4b2c12f | 2018-11-22 07:52:38 +0100 | [diff] [blame] | 241 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 242 | } |
| 243 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 244 | static void sc_read_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 245 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 246 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 247 | __FILE__, __func__, dev_name(dev)); |
| 248 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 249 | /* Get the normal PCI resources of this device. */ |
| 250 | pci_dev_read_resources(dev); |
| 251 | |
| 252 | /* Add non-standard MMIO resources. */ |
| 253 | sc_add_mmio_resources(dev); |
| 254 | |
| 255 | /* Add IO resources. */ |
| 256 | sc_add_io_resources(dev); |
| 257 | } |
| 258 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 259 | static void sc_init(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 260 | { |
| 261 | int i; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 262 | const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; |
| 263 | const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; |
| 264 | void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 265 | const struct soc_irq_route *ir = &global_soc_irq_route; |
| 266 | struct soc_intel_braswell_config *config = dev->chip_info; |
| 267 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 268 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 269 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 270 | |
| 271 | /* Set up the PIRQ PIC routing based on static config. */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 272 | for (i = 0; i < NUM_PIRQS; i++) |
| 273 | write8((void *)(pr_base + i*sizeof(ir->pic[i])), |
| 274 | ir->pic[i]); |
| 275 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 276 | /* Set up the per device PIRQ routing base on static config. */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 277 | for (i = 0; i < NUM_IR_DEVS; i++) |
| 278 | write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), |
| 279 | ir->pcidev[i]); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 280 | |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame^] | 281 | /* Interrupt 9 should be level triggered (SCI) */ |
| 282 | i8259_configure_irq_trigger(9, 1); |
| 283 | |
| 284 | for (i = 0; i < NUM_PIRQS; i++) { |
| 285 | if (ir->pic[i]) |
| 286 | i8259_configure_irq_trigger(ir->pic[i], 1); |
| 287 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 288 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 289 | if (config->disable_slp_x_stretch_sus_fail) { |
| 290 | printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); |
| 291 | write32(gen_pmcon1, |
| 292 | read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); |
| 293 | } else { |
| 294 | write32(gen_pmcon1, |
| 295 | read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); |
| 296 | } |
| 297 | |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame^] | 298 | /* Write IRQ assignments to PCI config space */ |
| 299 | write_pci_config_irqs(); |
| 300 | |
| 301 | /* Initialize i8259 pic */ |
| 302 | setup_i8259(); |
| 303 | |
Frans Hendriks | bd5233e | 2018-12-05 15:24:48 +0100 | [diff] [blame] | 304 | /* Initialize i8254 timers */ |
| 305 | setup_i8254(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | /* |
| 309 | * Common code for the south cluster devices. |
| 310 | */ |
| 311 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 312 | /* Set bit in function disble register to hide this device. */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 313 | static void sc_disable_devfn(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 314 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 315 | void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); |
| 316 | void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 317 | uint32_t mask = 0; |
| 318 | uint32_t mask2 = 0; |
| 319 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 320 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 321 | __FILE__, __func__, dev_name(dev)); |
| 322 | |
| 323 | #define SET_DIS_MASK(name_) \ |
| 324 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 325 | mask |= name_ ## _DIS |
| 326 | #define SET_DIS_MASK2(name_) \ |
| 327 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 328 | mask2 |= name_ ## _DIS |
| 329 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 330 | switch (dev->path.pci.devfn) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 331 | SET_DIS_MASK(SDIO); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 332 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 333 | SET_DIS_MASK(SD); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 334 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 335 | SET_DIS_MASK(SATA); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 336 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 337 | SET_DIS_MASK(XHCI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 338 | /* Disable super speed PHY when XHCI is not available. */ |
| 339 | mask2 |= USH_SS_PHY_DIS; |
| 340 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 341 | SET_DIS_MASK(LPE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 342 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 343 | SET_DIS_MASK(MMC); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 344 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 345 | SET_DIS_MASK(SIO_DMA1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 346 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 347 | SET_DIS_MASK(I2C1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 348 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 349 | SET_DIS_MASK(I2C2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 350 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 351 | SET_DIS_MASK(I2C3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 352 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 353 | SET_DIS_MASK(I2C4); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 354 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 355 | SET_DIS_MASK(I2C5); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 356 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 357 | SET_DIS_MASK(I2C6); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 358 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 359 | SET_DIS_MASK(I2C7); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 360 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 361 | SET_DIS_MASK(TXE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 362 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 363 | SET_DIS_MASK(HDA); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 364 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 365 | SET_DIS_MASK(PCIE_PORT1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 366 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 367 | SET_DIS_MASK(PCIE_PORT2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 368 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 369 | SET_DIS_MASK(PCIE_PORT3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 370 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 371 | SET_DIS_MASK(PCIE_PORT4); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 372 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 373 | SET_DIS_MASK(SIO_DMA2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 374 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 375 | SET_DIS_MASK(PWM1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 376 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 377 | SET_DIS_MASK(PWM2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 378 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 379 | SET_DIS_MASK(HSUART1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 380 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 381 | SET_DIS_MASK(HSUART2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 382 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 383 | SET_DIS_MASK(SPI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 384 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 385 | SET_DIS_MASK2(SMBUS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 386 | break; |
| 387 | } |
| 388 | |
| 389 | if (mask != 0) { |
| 390 | write32(func_dis, read32(func_dis) | mask); |
| 391 | /* Ensure posted write hits. */ |
| 392 | read32(func_dis); |
| 393 | } |
| 394 | |
| 395 | if (mask2 != 0) { |
| 396 | write32(func_dis2, read32(func_dis2) | mask2); |
| 397 | /* Ensure posted write hits. */ |
| 398 | read32(func_dis2); |
| 399 | } |
| 400 | } |
| 401 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 402 | static inline void set_d3hot_bits(struct device *dev, int offset) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 403 | { |
| 404 | uint32_t reg8; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 405 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 406 | printk(BIOS_SPEW, "%s/%s (%s, 0x%08x)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 407 | __FILE__, __func__, dev_name(dev), offset); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 408 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 409 | reg8 = pci_read_config8(dev, offset + 4); |
| 410 | reg8 |= 0x3; |
| 411 | pci_write_config8(dev, offset + 4, reg8); |
| 412 | } |
| 413 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 414 | /* |
| 415 | * Parts of the audio subsystem are powered by the HDA device. Therefore, one |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 416 | * cannot put HDA into D3Hot. Instead perform this workaround to make some of |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 417 | * the audio paths work for LPE audio. |
| 418 | */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 419 | static void hda_work_around(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 420 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 421 | void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); |
| 422 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 423 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 424 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 425 | |
| 426 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 427 | pci_write_config8(dev, 0x43, 0xd7); |
| 428 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 429 | /* |
| 430 | * Need to set bit 0 of GCTL to take the device out of reset. However, |
| 431 | * that requires setting up the 64-bit BAR. |
| 432 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 433 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 434 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
| 435 | pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
| 436 | write32(gctl, read32(gctl) | 0x1); |
| 437 | pci_write_config8(dev, PCI_COMMAND, 0); |
| 438 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 439 | } |
| 440 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 441 | static int place_device_in_d3hot(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 442 | { |
Lee Leahy | 1072e7d | 2017-03-16 17:35:32 -0700 | [diff] [blame] | 443 | unsigned int offset; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 444 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 445 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 446 | __FILE__, __func__, dev_name(dev)); |
| 447 | |
| 448 | /* |
| 449 | * Parts of the HDA block are used for LPE audio as well. |
| 450 | * Therefore assume the HDA will never be put into D3Hot. |
| 451 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 452 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 453 | hda_work_around(dev); |
| 454 | return 0; |
| 455 | } |
| 456 | |
| 457 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 458 | |
| 459 | if (offset != 0) { |
| 460 | set_d3hot_bits(dev, offset); |
| 461 | return 0; |
| 462 | } |
| 463 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 464 | /* |
| 465 | * For some reason some of the devices don't have the capability |
| 466 | * pointer set correctly. Work around this by hard coding the offset. |
| 467 | */ |
| 468 | #define DEV_CASE(name_) \ |
| 469 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) |
| 470 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 471 | switch (dev->path.pci.devfn) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 472 | DEV_CASE(SDIO) : |
| 473 | DEV_CASE(SD) : |
| 474 | DEV_CASE(MMC) : |
| 475 | DEV_CASE(LPE) : |
| 476 | DEV_CASE(SIO_DMA1) : |
| 477 | DEV_CASE(I2C1) : |
| 478 | DEV_CASE(I2C2) : |
| 479 | DEV_CASE(I2C3) : |
| 480 | DEV_CASE(I2C4) : |
| 481 | DEV_CASE(I2C5) : |
| 482 | DEV_CASE(I2C6) : |
| 483 | DEV_CASE(I2C7) : |
| 484 | DEV_CASE(SIO_DMA2) : |
| 485 | DEV_CASE(PWM1) : |
| 486 | DEV_CASE(PWM2) : |
| 487 | DEV_CASE(HSUART1) : |
| 488 | DEV_CASE(HSUART2) : |
| 489 | DEV_CASE(SPI) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 490 | offset = 0x80; |
| 491 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 492 | DEV_CASE(SATA) : |
| 493 | DEV_CASE(XHCI) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 494 | offset = 0x70; |
| 495 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 496 | DEV_CASE(HDA) : |
| 497 | DEV_CASE(SMBUS) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 498 | offset = 0x50; |
| 499 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 500 | DEV_CASE(TXE) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 501 | /* TXE cannot be placed in D3Hot. */ |
| 502 | return 0; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 503 | DEV_CASE(PCIE_PORT1) : |
| 504 | DEV_CASE(PCIE_PORT2) : |
| 505 | DEV_CASE(PCIE_PORT3) : |
| 506 | DEV_CASE(PCIE_PORT4) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 507 | offset = 0xa0; |
| 508 | break; |
| 509 | } |
| 510 | |
| 511 | if (offset != 0) { |
| 512 | set_d3hot_bits(dev, offset); |
| 513 | return 0; |
| 514 | } |
| 515 | |
| 516 | return -1; |
| 517 | } |
| 518 | |
| 519 | /* Common PCI device function disable. */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 520 | void southcluster_enable_dev(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 521 | { |
| 522 | uint32_t reg32; |
| 523 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 524 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 525 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 526 | if (!dev->enabled) { |
| 527 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 528 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 529 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 530 | dev_path(dev), slot, func); |
| 531 | |
| 532 | /* Ensure memory, io, and bus master are all disabled */ |
| 533 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 534 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 535 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 536 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 537 | |
| 538 | /* Place device in D3Hot */ |
| 539 | if (place_device_in_d3hot(dev) < 0) { |
| 540 | printk(BIOS_WARNING, |
| 541 | "Could not place %02x.%01x into D3Hot. " |
| 542 | "Keeping device visible.\n", slot, func); |
| 543 | return; |
| 544 | } |
| 545 | /* Disable this device if possible */ |
| 546 | sc_disable_devfn(dev); |
| 547 | } else { |
| 548 | /* Enable SERR */ |
| 549 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 550 | reg32 |= PCI_COMMAND_SERR; |
| 551 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | static struct device_operations device_ops = { |
| 556 | .read_resources = sc_read_resources, |
| 557 | .set_resources = pci_dev_set_resources, |
| 558 | .enable_resources = NULL, |
Lee Leahy | 2bc9cee | 2015-06-30 15:25:44 -0700 | [diff] [blame] | 559 | .acpi_inject_dsdt_generator = southcluster_inject_dsdt, |
| 560 | .write_acpi_tables = southcluster_write_acpi_tables, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 561 | .init = sc_init, |
| 562 | .enable = southcluster_enable_dev, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 563 | .scan_bus = scan_lpc_bus, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 564 | .ops_pci = &soc_pci_ops, |
| 565 | }; |
| 566 | |
| 567 | static const struct pci_driver southcluster __pci_driver = { |
| 568 | .ops = &device_ops, |
| 569 | .vendor = PCI_VENDOR_ID_INTEL, |
| 570 | .device = LPC_DEVID, |
| 571 | }; |
| 572 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 573 | int __weak mainboard_get_spi_config(struct spi_config *cfg) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 574 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 575 | printk(BIOS_SPEW, "%s/%s (0x%p)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 576 | __FILE__, __func__, (void *)cfg); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 577 | return -1; |
| 578 | } |
| 579 | |
| 580 | static void finalize_chipset(void *unused) |
| 581 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 582 | void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); |
| 583 | void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); |
| 584 | void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); |
| 585 | void *etr = (void *)(PMC_BASE_ADDRESS + ETR); |
| 586 | uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 587 | struct spi_config cfg; |
| 588 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 589 | printk(BIOS_SPEW, "%s/%s (0x%p)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 590 | __FILE__, __func__, unused); |
| 591 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 592 | /* Set the lock enable on the BIOS control register. */ |
| 593 | write32(bcr, read32(bcr) | BCR_LE); |
| 594 | |
| 595 | /* Set BIOS lock down bit controlling boot block size and swapping. */ |
| 596 | write32(gcs, read32(gcs) | BILD); |
| 597 | |
| 598 | /* Lock sleep stretching policy and set SMI lock. */ |
| 599 | write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); |
| 600 | |
| 601 | /* Set the CF9 lock. */ |
| 602 | write32(etr, read32(etr) | CF9LOCK); |
| 603 | |
| 604 | if (mainboard_get_spi_config(&cfg) < 0) { |
| 605 | printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); |
| 606 | } else { |
| 607 | write16(spi + PREOP, cfg.preop); |
| 608 | write16(spi + OPTYPE, cfg.optype); |
| 609 | write32(spi + OPMENU0, cfg.opmenu[0]); |
| 610 | write32(spi + OPMENU1, cfg.opmenu[1]); |
| 611 | write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); |
| 612 | write32(spi + UVSCC, cfg.uvscc); |
| 613 | write32(spi + LVSCC, cfg.lvscc | VCL); |
| 614 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 615 | spi_init(); |
Hannah Williams | 3fa80a9 | 2017-03-22 16:33:36 -0700 | [diff] [blame] | 616 | enable_serirq_quiet_mode(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 617 | |
| 618 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 619 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 620 | } |
| 621 | |
Hannah Williams | 2cfdde7 | 2015-04-15 19:48:07 -0700 | [diff] [blame] | 622 | BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, finalize_chipset, NULL); |