Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 6 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | #include <arch/io.h> |
| 19 | #include <arch/acpi.h> |
Lee Leahy | 2bc9cee | 2015-06-30 15:25:44 -0700 | [diff] [blame] | 20 | #include <arch/acpigen.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | #include <bootstate.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 22 | #include "chip.h" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 23 | #include <console/console.h> |
| 24 | #include <cpu/x86/smm.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 28 | #include <romstage_handoff.h> |
Lee Leahy | 2bc9cee | 2015-06-30 15:25:44 -0700 | [diff] [blame] | 29 | #include <soc/acpi.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | #include <soc/iomap.h> |
| 31 | #include <soc/irq.h> |
| 32 | #include <soc/lpc.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 34 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 35 | #include <soc/ramstage.h> |
| 36 | #include <soc/spi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 37 | #include <spi-generic.h> |
| 38 | #include <stdint.h> |
Hannah Williams | 3fa80a9 | 2017-03-22 16:33:36 -0700 | [diff] [blame] | 39 | #include <reg_script.h> |
| 40 | |
| 41 | static const struct reg_script ops[] = { |
| 42 | REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT, |
| 43 | ~SCNT_MODE, 0), /* put LPC SERIRQ in Quiet Mode */ |
| 44 | REG_SCRIPT_END |
| 45 | }; |
| 46 | |
| 47 | static void enable_serirq_quiet_mode(void) |
| 48 | { |
| 49 | reg_script_run(ops); |
| 50 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 51 | |
| 52 | static inline void |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 53 | add_mmio_resource(struct device *dev, int i, unsigned long addr, |
| 54 | unsigned long size) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 55 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 56 | printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 57 | __FILE__, __func__, dev_name(dev), addr, size); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 58 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 59 | } |
| 60 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 61 | static void sc_add_mmio_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 62 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 63 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 64 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 65 | add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 66 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 67 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 68 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 69 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 70 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 71 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 72 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
| 73 | } |
| 74 | |
| 75 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 76 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 77 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 78 | |
| 79 | static inline int io_range_in_default(int base, int size) |
| 80 | { |
| 81 | /* Does it start above the range? */ |
| 82 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 83 | return 0; |
| 84 | |
| 85 | /* Is it entirely contained? */ |
| 86 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 87 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 88 | return 1; |
| 89 | |
| 90 | /* This will return not in range for partial overlaps. */ |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * Note: this function assumes there is no overlap with the default LPC device's |
| 96 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 97 | */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 98 | static void sc_add_io_resource(struct device *dev, int base, int size, |
| 99 | int index) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 100 | { |
| 101 | struct resource *res; |
| 102 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 103 | printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x, 0x%08x)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 104 | __FILE__, __func__, dev_name(dev), base, size, index); |
| 105 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 106 | if (io_range_in_default(base, size)) |
| 107 | return; |
| 108 | |
| 109 | res = new_resource(dev, index); |
| 110 | res->base = base; |
| 111 | res->size = size; |
| 112 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 113 | } |
| 114 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 115 | static void sc_add_io_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 116 | { |
| 117 | struct resource *res; |
| 118 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 119 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 120 | __FILE__, __func__, dev_name(dev)); |
| 121 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 122 | /* Add the default claimed IO range for the LPC device. */ |
| 123 | res = new_resource(dev, 0); |
| 124 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 125 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 126 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 127 | |
| 128 | /* GPIO */ |
Frans Hendriks | 4b2c12f | 2018-11-22 07:52:38 +0100 | [diff] [blame^] | 129 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 130 | |
| 131 | /* ACPI */ |
Frans Hendriks | 4b2c12f | 2018-11-22 07:52:38 +0100 | [diff] [blame^] | 132 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 133 | } |
| 134 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 135 | static void sc_read_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 136 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 137 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 138 | __FILE__, __func__, dev_name(dev)); |
| 139 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 140 | /* Get the normal PCI resources of this device. */ |
| 141 | pci_dev_read_resources(dev); |
| 142 | |
| 143 | /* Add non-standard MMIO resources. */ |
| 144 | sc_add_mmio_resources(dev); |
| 145 | |
| 146 | /* Add IO resources. */ |
| 147 | sc_add_io_resources(dev); |
| 148 | } |
| 149 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 150 | static void sc_init(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 151 | { |
| 152 | int i; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 153 | const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; |
| 154 | const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; |
| 155 | void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); |
| 156 | void *actl = (void *)(ILB_BASE_ADDRESS + ACTL); |
| 157 | const struct soc_irq_route *ir = &global_soc_irq_route; |
| 158 | struct soc_intel_braswell_config *config = dev->chip_info; |
| 159 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 160 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 161 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 162 | |
| 163 | /* Set up the PIRQ PIC routing based on static config. */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 164 | for (i = 0; i < NUM_PIRQS; i++) |
| 165 | write8((void *)(pr_base + i*sizeof(ir->pic[i])), |
| 166 | ir->pic[i]); |
| 167 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 168 | /* Set up the per device PIRQ routing base on static config. */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 169 | for (i = 0; i < NUM_IR_DEVS; i++) |
| 170 | write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), |
| 171 | ir->pcidev[i]); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 172 | |
| 173 | /* Route SCI to IRQ9 */ |
| 174 | write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); |
| 175 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 176 | if (config->disable_slp_x_stretch_sus_fail) { |
| 177 | printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); |
| 178 | write32(gen_pmcon1, |
| 179 | read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); |
| 180 | } else { |
| 181 | write32(gen_pmcon1, |
| 182 | read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); |
| 183 | } |
| 184 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | /* |
| 188 | * Common code for the south cluster devices. |
| 189 | */ |
| 190 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 191 | /* Set bit in function disble register to hide this device. */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 192 | static void sc_disable_devfn(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 193 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 194 | void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); |
| 195 | void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 196 | uint32_t mask = 0; |
| 197 | uint32_t mask2 = 0; |
| 198 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 199 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 200 | __FILE__, __func__, dev_name(dev)); |
| 201 | |
| 202 | #define SET_DIS_MASK(name_) \ |
| 203 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 204 | mask |= name_ ## _DIS |
| 205 | #define SET_DIS_MASK2(name_) \ |
| 206 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 207 | mask2 |= name_ ## _DIS |
| 208 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 209 | switch (dev->path.pci.devfn) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 210 | SET_DIS_MASK(SDIO); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 211 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 212 | SET_DIS_MASK(SD); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 213 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 214 | SET_DIS_MASK(SATA); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 215 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 216 | SET_DIS_MASK(XHCI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 217 | /* Disable super speed PHY when XHCI is not available. */ |
| 218 | mask2 |= USH_SS_PHY_DIS; |
| 219 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 220 | SET_DIS_MASK(LPE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 221 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 222 | SET_DIS_MASK(MMC); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 223 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 224 | SET_DIS_MASK(SIO_DMA1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 225 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 226 | SET_DIS_MASK(I2C1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 227 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 228 | SET_DIS_MASK(I2C2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 229 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 230 | SET_DIS_MASK(I2C3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 231 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 232 | SET_DIS_MASK(I2C4); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 233 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 234 | SET_DIS_MASK(I2C5); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 235 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 236 | SET_DIS_MASK(I2C6); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 237 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 238 | SET_DIS_MASK(I2C7); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 239 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 240 | SET_DIS_MASK(TXE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 241 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 242 | SET_DIS_MASK(HDA); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 243 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 244 | SET_DIS_MASK(PCIE_PORT1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 245 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 246 | SET_DIS_MASK(PCIE_PORT2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 247 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 248 | SET_DIS_MASK(PCIE_PORT3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 249 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 250 | SET_DIS_MASK(PCIE_PORT4); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 251 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 252 | SET_DIS_MASK(SIO_DMA2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 253 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 254 | SET_DIS_MASK(PWM1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 255 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 256 | SET_DIS_MASK(PWM2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 257 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 258 | SET_DIS_MASK(HSUART1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 259 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 260 | SET_DIS_MASK(HSUART2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 261 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 262 | SET_DIS_MASK(SPI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 263 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 264 | SET_DIS_MASK2(SMBUS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 265 | break; |
| 266 | } |
| 267 | |
| 268 | if (mask != 0) { |
| 269 | write32(func_dis, read32(func_dis) | mask); |
| 270 | /* Ensure posted write hits. */ |
| 271 | read32(func_dis); |
| 272 | } |
| 273 | |
| 274 | if (mask2 != 0) { |
| 275 | write32(func_dis2, read32(func_dis2) | mask2); |
| 276 | /* Ensure posted write hits. */ |
| 277 | read32(func_dis2); |
| 278 | } |
| 279 | } |
| 280 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 281 | static inline void set_d3hot_bits(struct device *dev, int offset) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 282 | { |
| 283 | uint32_t reg8; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 284 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 285 | printk(BIOS_SPEW, "%s/%s (%s, 0x%08x)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 286 | __FILE__, __func__, dev_name(dev), offset); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 287 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 288 | reg8 = pci_read_config8(dev, offset + 4); |
| 289 | reg8 |= 0x3; |
| 290 | pci_write_config8(dev, offset + 4, reg8); |
| 291 | } |
| 292 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 293 | /* |
| 294 | * Parts of the audio subsystem are powered by the HDA device. Therefore, one |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 295 | * cannot put HDA into D3Hot. Instead perform this workaround to make some of |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 296 | * the audio paths work for LPE audio. |
| 297 | */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 298 | static void hda_work_around(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 299 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 300 | void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); |
| 301 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 302 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 303 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 304 | |
| 305 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 306 | pci_write_config8(dev, 0x43, 0xd7); |
| 307 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 308 | /* |
| 309 | * Need to set bit 0 of GCTL to take the device out of reset. However, |
| 310 | * that requires setting up the 64-bit BAR. |
| 311 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 312 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 313 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
| 314 | pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
| 315 | write32(gctl, read32(gctl) | 0x1); |
| 316 | pci_write_config8(dev, PCI_COMMAND, 0); |
| 317 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 318 | } |
| 319 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 320 | static int place_device_in_d3hot(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 321 | { |
Lee Leahy | 1072e7d | 2017-03-16 17:35:32 -0700 | [diff] [blame] | 322 | unsigned int offset; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 323 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 324 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 325 | __FILE__, __func__, dev_name(dev)); |
| 326 | |
| 327 | /* |
| 328 | * Parts of the HDA block are used for LPE audio as well. |
| 329 | * Therefore assume the HDA will never be put into D3Hot. |
| 330 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 331 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 332 | hda_work_around(dev); |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 337 | |
| 338 | if (offset != 0) { |
| 339 | set_d3hot_bits(dev, offset); |
| 340 | return 0; |
| 341 | } |
| 342 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 343 | /* |
| 344 | * For some reason some of the devices don't have the capability |
| 345 | * pointer set correctly. Work around this by hard coding the offset. |
| 346 | */ |
| 347 | #define DEV_CASE(name_) \ |
| 348 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) |
| 349 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 350 | switch (dev->path.pci.devfn) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 351 | DEV_CASE(SDIO) : |
| 352 | DEV_CASE(SD) : |
| 353 | DEV_CASE(MMC) : |
| 354 | DEV_CASE(LPE) : |
| 355 | DEV_CASE(SIO_DMA1) : |
| 356 | DEV_CASE(I2C1) : |
| 357 | DEV_CASE(I2C2) : |
| 358 | DEV_CASE(I2C3) : |
| 359 | DEV_CASE(I2C4) : |
| 360 | DEV_CASE(I2C5) : |
| 361 | DEV_CASE(I2C6) : |
| 362 | DEV_CASE(I2C7) : |
| 363 | DEV_CASE(SIO_DMA2) : |
| 364 | DEV_CASE(PWM1) : |
| 365 | DEV_CASE(PWM2) : |
| 366 | DEV_CASE(HSUART1) : |
| 367 | DEV_CASE(HSUART2) : |
| 368 | DEV_CASE(SPI) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 369 | offset = 0x80; |
| 370 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 371 | DEV_CASE(SATA) : |
| 372 | DEV_CASE(XHCI) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 373 | offset = 0x70; |
| 374 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 375 | DEV_CASE(HDA) : |
| 376 | DEV_CASE(SMBUS) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 377 | offset = 0x50; |
| 378 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 379 | DEV_CASE(TXE) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 380 | /* TXE cannot be placed in D3Hot. */ |
| 381 | return 0; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 382 | DEV_CASE(PCIE_PORT1) : |
| 383 | DEV_CASE(PCIE_PORT2) : |
| 384 | DEV_CASE(PCIE_PORT3) : |
| 385 | DEV_CASE(PCIE_PORT4) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 386 | offset = 0xa0; |
| 387 | break; |
| 388 | } |
| 389 | |
| 390 | if (offset != 0) { |
| 391 | set_d3hot_bits(dev, offset); |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | return -1; |
| 396 | } |
| 397 | |
| 398 | /* Common PCI device function disable. */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 399 | void southcluster_enable_dev(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 400 | { |
| 401 | uint32_t reg32; |
| 402 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 403 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 404 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 405 | if (!dev->enabled) { |
| 406 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 407 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 408 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 409 | dev_path(dev), slot, func); |
| 410 | |
| 411 | /* Ensure memory, io, and bus master are all disabled */ |
| 412 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 413 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 414 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 415 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 416 | |
| 417 | /* Place device in D3Hot */ |
| 418 | if (place_device_in_d3hot(dev) < 0) { |
| 419 | printk(BIOS_WARNING, |
| 420 | "Could not place %02x.%01x into D3Hot. " |
| 421 | "Keeping device visible.\n", slot, func); |
| 422 | return; |
| 423 | } |
| 424 | /* Disable this device if possible */ |
| 425 | sc_disable_devfn(dev); |
| 426 | } else { |
| 427 | /* Enable SERR */ |
| 428 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 429 | reg32 |= PCI_COMMAND_SERR; |
| 430 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 431 | } |
| 432 | } |
| 433 | |
| 434 | static struct device_operations device_ops = { |
| 435 | .read_resources = sc_read_resources, |
| 436 | .set_resources = pci_dev_set_resources, |
| 437 | .enable_resources = NULL, |
Lee Leahy | 2bc9cee | 2015-06-30 15:25:44 -0700 | [diff] [blame] | 438 | .acpi_inject_dsdt_generator = southcluster_inject_dsdt, |
| 439 | .write_acpi_tables = southcluster_write_acpi_tables, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 440 | .init = sc_init, |
| 441 | .enable = southcluster_enable_dev, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 442 | .scan_bus = scan_lpc_bus, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 443 | .ops_pci = &soc_pci_ops, |
| 444 | }; |
| 445 | |
| 446 | static const struct pci_driver southcluster __pci_driver = { |
| 447 | .ops = &device_ops, |
| 448 | .vendor = PCI_VENDOR_ID_INTEL, |
| 449 | .device = LPC_DEVID, |
| 450 | }; |
| 451 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 452 | int __weak mainboard_get_spi_config(struct spi_config *cfg) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 453 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 454 | printk(BIOS_SPEW, "%s/%s (0x%p)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 455 | __FILE__, __func__, (void *)cfg); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 456 | return -1; |
| 457 | } |
| 458 | |
| 459 | static void finalize_chipset(void *unused) |
| 460 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 461 | void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); |
| 462 | void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); |
| 463 | void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); |
| 464 | void *etr = (void *)(PMC_BASE_ADDRESS + ETR); |
| 465 | uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 466 | struct spi_config cfg; |
| 467 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 468 | printk(BIOS_SPEW, "%s/%s (0x%p)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 469 | __FILE__, __func__, unused); |
| 470 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 471 | /* Set the lock enable on the BIOS control register. */ |
| 472 | write32(bcr, read32(bcr) | BCR_LE); |
| 473 | |
| 474 | /* Set BIOS lock down bit controlling boot block size and swapping. */ |
| 475 | write32(gcs, read32(gcs) | BILD); |
| 476 | |
| 477 | /* Lock sleep stretching policy and set SMI lock. */ |
| 478 | write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); |
| 479 | |
| 480 | /* Set the CF9 lock. */ |
| 481 | write32(etr, read32(etr) | CF9LOCK); |
| 482 | |
| 483 | if (mainboard_get_spi_config(&cfg) < 0) { |
| 484 | printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); |
| 485 | } else { |
| 486 | write16(spi + PREOP, cfg.preop); |
| 487 | write16(spi + OPTYPE, cfg.optype); |
| 488 | write32(spi + OPMENU0, cfg.opmenu[0]); |
| 489 | write32(spi + OPMENU1, cfg.opmenu[1]); |
| 490 | write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); |
| 491 | write32(spi + UVSCC, cfg.uvscc); |
| 492 | write32(spi + LVSCC, cfg.lvscc | VCL); |
| 493 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 494 | spi_init(); |
Hannah Williams | 3fa80a9 | 2017-03-22 16:33:36 -0700 | [diff] [blame] | 495 | enable_serirq_quiet_mode(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 496 | |
| 497 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 498 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 499 | } |
| 500 | |
Hannah Williams | 2cfdde7 | 2015-04-15 19:48:07 -0700 | [diff] [blame] | 501 | BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, finalize_chipset, NULL); |