Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 6 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
Patrick Georgi | 25509ee | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 19 | * Foundation, Inc. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | */ |
| 21 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | #include <arch/io.h> |
| 23 | #include <arch/acpi.h> |
| 24 | #include <bootstate.h> |
| 25 | #include <cbmem.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 26 | #include "chip.h" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 27 | #include <console/console.h> |
| 28 | #include <cpu/x86/smm.h> |
| 29 | #include <device/device.h> |
| 30 | #include <device/pci.h> |
| 31 | #include <device/pci_ids.h> |
| 32 | #include <pc80/mc146818rtc.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 33 | #include <romstage_handoff.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 34 | #include <soc/iomap.h> |
| 35 | #include <soc/irq.h> |
| 36 | #include <soc/lpc.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 37 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 38 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 39 | #include <soc/ramstage.h> |
| 40 | #include <soc/spi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 41 | #include <spi-generic.h> |
| 42 | #include <stdint.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 43 | |
| 44 | static inline void |
| 45 | add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) |
| 46 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 47 | printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n", |
| 48 | __FILE__, __func__, dev_name(dev), addr, size); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 49 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 50 | } |
| 51 | |
| 52 | static void sc_add_mmio_resources(device_t dev) |
| 53 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 54 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 55 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 56 | add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 57 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 58 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 59 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 60 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 61 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 62 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 63 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
| 64 | } |
| 65 | |
| 66 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 67 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 68 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 69 | |
| 70 | static inline int io_range_in_default(int base, int size) |
| 71 | { |
| 72 | /* Does it start above the range? */ |
| 73 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 74 | return 0; |
| 75 | |
| 76 | /* Is it entirely contained? */ |
| 77 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 78 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 79 | return 1; |
| 80 | |
| 81 | /* This will return not in range for partial overlaps. */ |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | /* |
| 86 | * Note: this function assumes there is no overlap with the default LPC device's |
| 87 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 88 | */ |
| 89 | static void sc_add_io_resource(device_t dev, int base, int size, int index) |
| 90 | { |
| 91 | struct resource *res; |
| 92 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 93 | printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x, 0x%08x )\n", |
| 94 | __FILE__, __func__, dev_name(dev), base, size, index); |
| 95 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 96 | if (io_range_in_default(base, size)) |
| 97 | return; |
| 98 | |
| 99 | res = new_resource(dev, index); |
| 100 | res->base = base; |
| 101 | res->size = size; |
| 102 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 103 | } |
| 104 | |
| 105 | static void sc_add_io_resources(device_t dev) |
| 106 | { |
| 107 | struct resource *res; |
| 108 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 109 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 110 | __FILE__, __func__, dev_name(dev)); |
| 111 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 112 | /* Add the default claimed IO range for the LPC device. */ |
| 113 | res = new_resource(dev, 0); |
| 114 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 115 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 116 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 117 | |
| 118 | /* GPIO */ |
| 119 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); |
| 120 | |
| 121 | /* ACPI */ |
| 122 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); |
| 123 | } |
| 124 | |
| 125 | static void sc_read_resources(device_t dev) |
| 126 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 127 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 128 | __FILE__, __func__, dev_name(dev)); |
| 129 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 130 | /* Get the normal PCI resources of this device. */ |
| 131 | pci_dev_read_resources(dev); |
| 132 | |
| 133 | /* Add non-standard MMIO resources. */ |
| 134 | sc_add_mmio_resources(dev); |
| 135 | |
| 136 | /* Add IO resources. */ |
| 137 | sc_add_io_resources(dev); |
| 138 | } |
| 139 | |
| 140 | static void sc_rtc_init(void) |
| 141 | { |
| 142 | uint32_t gen_pmcon1; |
| 143 | int rtc_fail; |
| 144 | struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 145 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 146 | printk(BIOS_SPEW, "%s/%s\n", |
| 147 | __FILE__, __func__); |
| 148 | if (ps != NULL) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 149 | gen_pmcon1 = ps->gen_pmcon1; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 150 | else |
| 151 | gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 152 | |
| 153 | rtc_fail = !!(gen_pmcon1 & RPS); |
| 154 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 155 | if (rtc_fail) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 156 | printk(BIOS_DEBUG, "RTC failure.\n"); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 157 | |
| 158 | cmos_init(rtc_fail); |
| 159 | } |
| 160 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 161 | static void sc_init(device_t dev) |
| 162 | { |
| 163 | int i; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 164 | const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; |
| 165 | const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; |
| 166 | void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); |
| 167 | void *actl = (void *)(ILB_BASE_ADDRESS + ACTL); |
| 168 | const struct soc_irq_route *ir = &global_soc_irq_route; |
| 169 | struct soc_intel_braswell_config *config = dev->chip_info; |
| 170 | |
| 171 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 172 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 173 | |
| 174 | /* Set up the PIRQ PIC routing based on static config. */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 175 | for (i = 0; i < NUM_PIRQS; i++) |
| 176 | write8((void *)(pr_base + i*sizeof(ir->pic[i])), |
| 177 | ir->pic[i]); |
| 178 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 179 | /* Set up the per device PIRQ routing base on static config. */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 180 | for (i = 0; i < NUM_IR_DEVS; i++) |
| 181 | write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), |
| 182 | ir->pcidev[i]); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 183 | |
| 184 | /* Route SCI to IRQ9 */ |
| 185 | write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); |
| 186 | |
| 187 | sc_rtc_init(); |
| 188 | |
| 189 | if (config->disable_slp_x_stretch_sus_fail) { |
| 190 | printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); |
| 191 | write32(gen_pmcon1, |
| 192 | read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); |
| 193 | } else { |
| 194 | write32(gen_pmcon1, |
| 195 | read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); |
| 196 | } |
| 197 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | /* |
| 201 | * Common code for the south cluster devices. |
| 202 | */ |
| 203 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 204 | /* Set bit in function disble register to hide this device. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 205 | static void sc_disable_devfn(device_t dev) |
| 206 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 207 | void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); |
| 208 | void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 209 | uint32_t mask = 0; |
| 210 | uint32_t mask2 = 0; |
| 211 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 212 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 213 | __FILE__, __func__, dev_name(dev)); |
| 214 | |
| 215 | #define SET_DIS_MASK(name_) \ |
| 216 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 217 | mask |= name_ ## _DIS |
| 218 | #define SET_DIS_MASK2(name_) \ |
| 219 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 220 | mask2 |= name_ ## _DIS |
| 221 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 222 | switch (dev->path.pci.devfn) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 223 | SET_DIS_MASK(SDIO); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 224 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 225 | SET_DIS_MASK(SD); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 226 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 227 | SET_DIS_MASK(SATA); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 228 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 229 | SET_DIS_MASK(XHCI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 230 | /* Disable super speed PHY when XHCI is not available. */ |
| 231 | mask2 |= USH_SS_PHY_DIS; |
| 232 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 233 | SET_DIS_MASK(LPE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 234 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 235 | SET_DIS_MASK(MMC); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 236 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 237 | SET_DIS_MASK(SIO_DMA1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 238 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 239 | SET_DIS_MASK(I2C1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 240 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 241 | SET_DIS_MASK(I2C2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 242 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 243 | SET_DIS_MASK(I2C3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 244 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 245 | SET_DIS_MASK(I2C4); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 246 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 247 | SET_DIS_MASK(I2C5); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 248 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 249 | SET_DIS_MASK(I2C6); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 250 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 251 | SET_DIS_MASK(I2C7); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 252 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 253 | SET_DIS_MASK(TXE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 254 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 255 | SET_DIS_MASK(HDA); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 256 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 257 | SET_DIS_MASK(PCIE_PORT1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 258 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 259 | SET_DIS_MASK(PCIE_PORT2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 260 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 261 | SET_DIS_MASK(PCIE_PORT3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 262 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 263 | SET_DIS_MASK(PCIE_PORT4); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 264 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 265 | SET_DIS_MASK(SIO_DMA2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 266 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 267 | SET_DIS_MASK(PWM1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 268 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 269 | SET_DIS_MASK(PWM2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 270 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 271 | SET_DIS_MASK(HSUART1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 272 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 273 | SET_DIS_MASK(HSUART2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 274 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 275 | SET_DIS_MASK(SPI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 276 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 277 | SET_DIS_MASK2(SMBUS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 278 | break; |
| 279 | } |
| 280 | |
| 281 | if (mask != 0) { |
| 282 | write32(func_dis, read32(func_dis) | mask); |
| 283 | /* Ensure posted write hits. */ |
| 284 | read32(func_dis); |
| 285 | } |
| 286 | |
| 287 | if (mask2 != 0) { |
| 288 | write32(func_dis2, read32(func_dis2) | mask2); |
| 289 | /* Ensure posted write hits. */ |
| 290 | read32(func_dis2); |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | static inline void set_d3hot_bits(device_t dev, int offset) |
| 295 | { |
| 296 | uint32_t reg8; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 297 | |
| 298 | printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x )\n", |
| 299 | __FILE__, __func__, dev_name(dev), offset); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 300 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 301 | reg8 = pci_read_config8(dev, offset + 4); |
| 302 | reg8 |= 0x3; |
| 303 | pci_write_config8(dev, offset + 4, reg8); |
| 304 | } |
| 305 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 306 | /* |
| 307 | * Parts of the audio subsystem are powered by the HDA device. Therefore, one |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 308 | * cannot put HDA into D3Hot. Instead perform this workaround to make some of |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 309 | * the audio paths work for LPE audio. |
| 310 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 311 | static void hda_work_around(device_t dev) |
| 312 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 313 | void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); |
| 314 | |
| 315 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 316 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 317 | |
| 318 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 319 | pci_write_config8(dev, 0x43, 0xd7); |
| 320 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 321 | /* |
| 322 | * Need to set bit 0 of GCTL to take the device out of reset. However, |
| 323 | * that requires setting up the 64-bit BAR. |
| 324 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 325 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 326 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
| 327 | pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
| 328 | write32(gctl, read32(gctl) | 0x1); |
| 329 | pci_write_config8(dev, PCI_COMMAND, 0); |
| 330 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 331 | } |
| 332 | |
| 333 | static int place_device_in_d3hot(device_t dev) |
| 334 | { |
| 335 | unsigned offset; |
| 336 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 337 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 338 | __FILE__, __func__, dev_name(dev)); |
| 339 | |
| 340 | /* |
| 341 | * Parts of the HDA block are used for LPE audio as well. |
| 342 | * Therefore assume the HDA will never be put into D3Hot. |
| 343 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 344 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 345 | hda_work_around(dev); |
| 346 | return 0; |
| 347 | } |
| 348 | |
| 349 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 350 | |
| 351 | if (offset != 0) { |
| 352 | set_d3hot_bits(dev, offset); |
| 353 | return 0; |
| 354 | } |
| 355 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 356 | /* |
| 357 | * For some reason some of the devices don't have the capability |
| 358 | * pointer set correctly. Work around this by hard coding the offset. |
| 359 | */ |
| 360 | #define DEV_CASE(name_) \ |
| 361 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) |
| 362 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 363 | switch (dev->path.pci.devfn) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 364 | DEV_CASE(SDIO) : |
| 365 | DEV_CASE(SD) : |
| 366 | DEV_CASE(MMC) : |
| 367 | DEV_CASE(LPE) : |
| 368 | DEV_CASE(SIO_DMA1) : |
| 369 | DEV_CASE(I2C1) : |
| 370 | DEV_CASE(I2C2) : |
| 371 | DEV_CASE(I2C3) : |
| 372 | DEV_CASE(I2C4) : |
| 373 | DEV_CASE(I2C5) : |
| 374 | DEV_CASE(I2C6) : |
| 375 | DEV_CASE(I2C7) : |
| 376 | DEV_CASE(SIO_DMA2) : |
| 377 | DEV_CASE(PWM1) : |
| 378 | DEV_CASE(PWM2) : |
| 379 | DEV_CASE(HSUART1) : |
| 380 | DEV_CASE(HSUART2) : |
| 381 | DEV_CASE(SPI) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 382 | offset = 0x80; |
| 383 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 384 | DEV_CASE(SATA) : |
| 385 | DEV_CASE(XHCI) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 386 | offset = 0x70; |
| 387 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 388 | DEV_CASE(HDA) : |
| 389 | DEV_CASE(SMBUS) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 390 | offset = 0x50; |
| 391 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 392 | DEV_CASE(TXE) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 393 | /* TXE cannot be placed in D3Hot. */ |
| 394 | return 0; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 395 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 396 | DEV_CASE(PCIE_PORT1) : |
| 397 | DEV_CASE(PCIE_PORT2) : |
| 398 | DEV_CASE(PCIE_PORT3) : |
| 399 | DEV_CASE(PCIE_PORT4) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 400 | offset = 0xa0; |
| 401 | break; |
| 402 | } |
| 403 | |
| 404 | if (offset != 0) { |
| 405 | set_d3hot_bits(dev, offset); |
| 406 | return 0; |
| 407 | } |
| 408 | |
| 409 | return -1; |
| 410 | } |
| 411 | |
| 412 | /* Common PCI device function disable. */ |
| 413 | void southcluster_enable_dev(device_t dev) |
| 414 | { |
| 415 | uint32_t reg32; |
| 416 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 417 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 418 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 419 | if (!dev->enabled) { |
| 420 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 421 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 422 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 423 | dev_path(dev), slot, func); |
| 424 | |
| 425 | /* Ensure memory, io, and bus master are all disabled */ |
| 426 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 427 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 428 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 429 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 430 | |
| 431 | /* Place device in D3Hot */ |
| 432 | if (place_device_in_d3hot(dev) < 0) { |
| 433 | printk(BIOS_WARNING, |
| 434 | "Could not place %02x.%01x into D3Hot. " |
| 435 | "Keeping device visible.\n", slot, func); |
| 436 | return; |
| 437 | } |
| 438 | /* Disable this device if possible */ |
| 439 | sc_disable_devfn(dev); |
| 440 | } else { |
| 441 | /* Enable SERR */ |
| 442 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 443 | reg32 |= PCI_COMMAND_SERR; |
| 444 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | static struct device_operations device_ops = { |
| 449 | .read_resources = sc_read_resources, |
| 450 | .set_resources = pci_dev_set_resources, |
| 451 | .enable_resources = NULL, |
| 452 | .init = sc_init, |
| 453 | .enable = southcluster_enable_dev, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 454 | .scan_bus = scan_lpc_bus, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 455 | .ops_pci = &soc_pci_ops, |
| 456 | }; |
| 457 | |
| 458 | static const struct pci_driver southcluster __pci_driver = { |
| 459 | .ops = &device_ops, |
| 460 | .vendor = PCI_VENDOR_ID_INTEL, |
| 461 | .device = LPC_DEVID, |
| 462 | }; |
| 463 | |
| 464 | int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) |
| 465 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 466 | printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", |
| 467 | __FILE__, __func__, (void *)cfg); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 468 | return -1; |
| 469 | } |
| 470 | |
| 471 | static void finalize_chipset(void *unused) |
| 472 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 473 | void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); |
| 474 | void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); |
| 475 | void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); |
| 476 | void *etr = (void *)(PMC_BASE_ADDRESS + ETR); |
| 477 | uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 478 | struct spi_config cfg; |
| 479 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 480 | printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", |
| 481 | __FILE__, __func__, unused); |
| 482 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 483 | /* Set the lock enable on the BIOS control register. */ |
| 484 | write32(bcr, read32(bcr) | BCR_LE); |
| 485 | |
| 486 | /* Set BIOS lock down bit controlling boot block size and swapping. */ |
| 487 | write32(gcs, read32(gcs) | BILD); |
| 488 | |
| 489 | /* Lock sleep stretching policy and set SMI lock. */ |
| 490 | write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); |
| 491 | |
| 492 | /* Set the CF9 lock. */ |
| 493 | write32(etr, read32(etr) | CF9LOCK); |
| 494 | |
| 495 | if (mainboard_get_spi_config(&cfg) < 0) { |
| 496 | printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); |
| 497 | } else { |
| 498 | write16(spi + PREOP, cfg.preop); |
| 499 | write16(spi + OPTYPE, cfg.optype); |
| 500 | write32(spi + OPMENU0, cfg.opmenu[0]); |
| 501 | write32(spi + OPMENU1, cfg.opmenu[1]); |
| 502 | write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); |
| 503 | write32(spi + UVSCC, cfg.uvscc); |
| 504 | write32(spi + LVSCC, cfg.lvscc | VCL); |
| 505 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 506 | spi_init(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 507 | |
| 508 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 509 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 510 | } |
| 511 | |
| 512 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); |
| 513 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); |