blob: 05fa855dc642a56cff1662fa6e41012fcb204144 [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07006 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070016 */
17
Lee Leahy77ff0b12015-05-05 15:07:29 -070018#include <arch/io.h>
19#include <arch/acpi.h>
Lee Leahy2bc9cee2015-06-30 15:25:44 -070020#include <arch/acpigen.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070021#include <bootstate.h>
22#include <cbmem.h>
Lee Leahy32471722015-04-20 15:20:28 -070023#include "chip.h"
Aaron Durbin64031672018-04-21 14:45:32 -060024#include <compiler.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070025#include <console/console.h>
26#include <cpu/x86/smm.h>
27#include <device/device.h>
28#include <device/pci.h>
29#include <device/pci_ids.h>
30#include <pc80/mc146818rtc.h>
Lee Leahy32471722015-04-20 15:20:28 -070031#include <romstage_handoff.h>
Lee Leahy2bc9cee2015-06-30 15:25:44 -070032#include <soc/acpi.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070033#include <soc/iomap.h>
34#include <soc/irq.h>
35#include <soc/lpc.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070036#include <soc/pci_devs.h>
Lee Leahy32471722015-04-20 15:20:28 -070037#include <soc/pm.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070038#include <soc/ramstage.h>
39#include <soc/spi.h>
Lee Leahy32471722015-04-20 15:20:28 -070040#include <spi-generic.h>
41#include <stdint.h>
Hannah Williams3fa80a92017-03-22 16:33:36 -070042#include <reg_script.h>
43
44static const struct reg_script ops[] = {
45 REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT,
46 ~SCNT_MODE, 0), /* put LPC SERIRQ in Quiet Mode */
47 REG_SCRIPT_END
48};
49
50static void enable_serirq_quiet_mode(void)
51{
52 reg_script_run(ops);
53}
Lee Leahy77ff0b12015-05-05 15:07:29 -070054
55static inline void
56add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
57{
Lee Leahy32471722015-04-20 15:20:28 -070058 printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n",
59 __FILE__, __func__, dev_name(dev), addr, size);
Lee Leahy77ff0b12015-05-05 15:07:29 -070060 mmio_resource(dev, i, addr >> 10, size >> 10);
61}
62
63static void sc_add_mmio_resources(device_t dev)
64{
Lee Leahy32471722015-04-20 15:20:28 -070065 printk(BIOS_SPEW, "%s/%s ( %s )\n",
66 __FILE__, __func__, dev_name(dev));
Lee Leahy77ff0b12015-05-05 15:07:29 -070067 add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
68 add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
69 add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
70 add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
71 add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
72 add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
73 add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
74 add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
75}
76
77/* Default IO range claimed by the LPC device. The upper bound is exclusive. */
78#define LPC_DEFAULT_IO_RANGE_LOWER 0
79#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
80
81static inline int io_range_in_default(int base, int size)
82{
83 /* Does it start above the range? */
84 if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
85 return 0;
86
87 /* Is it entirely contained? */
88 if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
89 (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
90 return 1;
91
92 /* This will return not in range for partial overlaps. */
93 return 0;
94}
95
96/*
97 * Note: this function assumes there is no overlap with the default LPC device's
98 * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
99 */
100static void sc_add_io_resource(device_t dev, int base, int size, int index)
101{
102 struct resource *res;
103
Lee Leahy32471722015-04-20 15:20:28 -0700104 printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x, 0x%08x )\n",
105 __FILE__, __func__, dev_name(dev), base, size, index);
106
Lee Leahy77ff0b12015-05-05 15:07:29 -0700107 if (io_range_in_default(base, size))
108 return;
109
110 res = new_resource(dev, index);
111 res->base = base;
112 res->size = size;
113 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
114}
115
116static void sc_add_io_resources(device_t dev)
117{
118 struct resource *res;
119
Lee Leahy32471722015-04-20 15:20:28 -0700120 printk(BIOS_SPEW, "%s/%s ( %s )\n",
121 __FILE__, __func__, dev_name(dev));
122
Lee Leahy77ff0b12015-05-05 15:07:29 -0700123 /* Add the default claimed IO range for the LPC device. */
124 res = new_resource(dev, 0);
125 res->base = LPC_DEFAULT_IO_RANGE_LOWER;
126 res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
127 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
128
129 /* GPIO */
130 sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE);
131
132 /* ACPI */
133 sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
134}
135
136static void sc_read_resources(device_t dev)
137{
Lee Leahy32471722015-04-20 15:20:28 -0700138 printk(BIOS_SPEW, "%s/%s ( %s )\n",
139 __FILE__, __func__, dev_name(dev));
140
Lee Leahy77ff0b12015-05-05 15:07:29 -0700141 /* Get the normal PCI resources of this device. */
142 pci_dev_read_resources(dev);
143
144 /* Add non-standard MMIO resources. */
145 sc_add_mmio_resources(dev);
146
147 /* Add IO resources. */
148 sc_add_io_resources(dev);
149}
150
151static void sc_rtc_init(void)
152{
Aaron Durbinb19e33f2017-09-15 14:32:13 -0600153 printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__);
154 cmos_init(rtc_failure());
Lee Leahy77ff0b12015-05-05 15:07:29 -0700155}
156
Lee Leahy77ff0b12015-05-05 15:07:29 -0700157static void sc_init(device_t dev)
158{
159 int i;
Lee Leahy32471722015-04-20 15:20:28 -0700160 const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
161 const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
162 void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1);
163 void *actl = (void *)(ILB_BASE_ADDRESS + ACTL);
164 const struct soc_irq_route *ir = &global_soc_irq_route;
165 struct soc_intel_braswell_config *config = dev->chip_info;
166
167 printk(BIOS_SPEW, "%s/%s ( %s )\n",
168 __FILE__, __func__, dev_name(dev));
Lee Leahy77ff0b12015-05-05 15:07:29 -0700169
170 /* Set up the PIRQ PIC routing based on static config. */
Lee Leahy32471722015-04-20 15:20:28 -0700171 for (i = 0; i < NUM_PIRQS; i++)
172 write8((void *)(pr_base + i*sizeof(ir->pic[i])),
173 ir->pic[i]);
174
Lee Leahy77ff0b12015-05-05 15:07:29 -0700175 /* Set up the per device PIRQ routing base on static config. */
Lee Leahy32471722015-04-20 15:20:28 -0700176 for (i = 0; i < NUM_IR_DEVS; i++)
177 write16((void *)(ir_base + i*sizeof(ir->pcidev[i])),
178 ir->pcidev[i]);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700179
180 /* Route SCI to IRQ9 */
181 write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
182
183 sc_rtc_init();
184
185 if (config->disable_slp_x_stretch_sus_fail) {
186 printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
187 write32(gen_pmcon1,
188 read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
189 } else {
190 write32(gen_pmcon1,
191 read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
192 }
193
Lee Leahy77ff0b12015-05-05 15:07:29 -0700194}
195
196/*
197 * Common code for the south cluster devices.
198 */
199
Lee Leahy32471722015-04-20 15:20:28 -0700200/* Set bit in function disble register to hide this device. */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700201static void sc_disable_devfn(device_t dev)
202{
Lee Leahy32471722015-04-20 15:20:28 -0700203 void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
204 void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700205 uint32_t mask = 0;
206 uint32_t mask2 = 0;
207
Lee Leahy32471722015-04-20 15:20:28 -0700208 printk(BIOS_SPEW, "%s/%s ( %s )\n",
209 __FILE__, __func__, dev_name(dev));
210
211#define SET_DIS_MASK(name_) \
212 case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
213 mask |= name_ ## _DIS
214#define SET_DIS_MASK2(name_) \
215 case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
216 mask2 |= name_ ## _DIS
217
Lee Leahy77ff0b12015-05-05 15:07:29 -0700218 switch (dev->path.pci.devfn) {
Lee Leahy32471722015-04-20 15:20:28 -0700219 SET_DIS_MASK(SDIO);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700220 break;
Lee Leahy32471722015-04-20 15:20:28 -0700221 SET_DIS_MASK(SD);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700222 break;
Lee Leahy32471722015-04-20 15:20:28 -0700223 SET_DIS_MASK(SATA);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700224 break;
Lee Leahy32471722015-04-20 15:20:28 -0700225 SET_DIS_MASK(XHCI);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700226 /* Disable super speed PHY when XHCI is not available. */
227 mask2 |= USH_SS_PHY_DIS;
228 break;
Lee Leahy32471722015-04-20 15:20:28 -0700229 SET_DIS_MASK(LPE);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700230 break;
Lee Leahy32471722015-04-20 15:20:28 -0700231 SET_DIS_MASK(MMC);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700232 break;
Lee Leahy32471722015-04-20 15:20:28 -0700233 SET_DIS_MASK(SIO_DMA1);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700234 break;
Lee Leahy32471722015-04-20 15:20:28 -0700235 SET_DIS_MASK(I2C1);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700236 break;
Lee Leahy32471722015-04-20 15:20:28 -0700237 SET_DIS_MASK(I2C2);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700238 break;
Lee Leahy32471722015-04-20 15:20:28 -0700239 SET_DIS_MASK(I2C3);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700240 break;
Lee Leahy32471722015-04-20 15:20:28 -0700241 SET_DIS_MASK(I2C4);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700242 break;
Lee Leahy32471722015-04-20 15:20:28 -0700243 SET_DIS_MASK(I2C5);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700244 break;
Lee Leahy32471722015-04-20 15:20:28 -0700245 SET_DIS_MASK(I2C6);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700246 break;
Lee Leahy32471722015-04-20 15:20:28 -0700247 SET_DIS_MASK(I2C7);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700248 break;
Lee Leahy32471722015-04-20 15:20:28 -0700249 SET_DIS_MASK(TXE);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700250 break;
Lee Leahy32471722015-04-20 15:20:28 -0700251 SET_DIS_MASK(HDA);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700252 break;
Lee Leahy32471722015-04-20 15:20:28 -0700253 SET_DIS_MASK(PCIE_PORT1);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700254 break;
Lee Leahy32471722015-04-20 15:20:28 -0700255 SET_DIS_MASK(PCIE_PORT2);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700256 break;
Lee Leahy32471722015-04-20 15:20:28 -0700257 SET_DIS_MASK(PCIE_PORT3);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700258 break;
Lee Leahy32471722015-04-20 15:20:28 -0700259 SET_DIS_MASK(PCIE_PORT4);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700260 break;
Lee Leahy32471722015-04-20 15:20:28 -0700261 SET_DIS_MASK(SIO_DMA2);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700262 break;
Lee Leahy32471722015-04-20 15:20:28 -0700263 SET_DIS_MASK(PWM1);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700264 break;
Lee Leahy32471722015-04-20 15:20:28 -0700265 SET_DIS_MASK(PWM2);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700266 break;
Lee Leahy32471722015-04-20 15:20:28 -0700267 SET_DIS_MASK(HSUART1);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700268 break;
Lee Leahy32471722015-04-20 15:20:28 -0700269 SET_DIS_MASK(HSUART2);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700270 break;
Lee Leahy32471722015-04-20 15:20:28 -0700271 SET_DIS_MASK(SPI);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700272 break;
Lee Leahy32471722015-04-20 15:20:28 -0700273 SET_DIS_MASK2(SMBUS);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700274 break;
275 }
276
277 if (mask != 0) {
278 write32(func_dis, read32(func_dis) | mask);
279 /* Ensure posted write hits. */
280 read32(func_dis);
281 }
282
283 if (mask2 != 0) {
284 write32(func_dis2, read32(func_dis2) | mask2);
285 /* Ensure posted write hits. */
286 read32(func_dis2);
287 }
288}
289
290static inline void set_d3hot_bits(device_t dev, int offset)
291{
292 uint32_t reg8;
Lee Leahy32471722015-04-20 15:20:28 -0700293
294 printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x )\n",
295 __FILE__, __func__, dev_name(dev), offset);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700296 printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
297 reg8 = pci_read_config8(dev, offset + 4);
298 reg8 |= 0x3;
299 pci_write_config8(dev, offset + 4, reg8);
300}
301
Lee Leahy32471722015-04-20 15:20:28 -0700302/*
303 * Parts of the audio subsystem are powered by the HDA device. Therefore, one
Lee Leahy77ff0b12015-05-05 15:07:29 -0700304 * cannot put HDA into D3Hot. Instead perform this workaround to make some of
Lee Leahy32471722015-04-20 15:20:28 -0700305 * the audio paths work for LPE audio.
306 */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700307static void hda_work_around(device_t dev)
308{
Lee Leahy32471722015-04-20 15:20:28 -0700309 void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
310
311 printk(BIOS_SPEW, "%s/%s ( %s )\n",
312 __FILE__, __func__, dev_name(dev));
Lee Leahy77ff0b12015-05-05 15:07:29 -0700313
314 /* Need to set magic register 0x43 to 0xd7 in config space. */
315 pci_write_config8(dev, 0x43, 0xd7);
316
Lee Leahy32471722015-04-20 15:20:28 -0700317 /*
318 * Need to set bit 0 of GCTL to take the device out of reset. However,
319 * that requires setting up the 64-bit BAR.
320 */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700321 pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
322 pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
323 pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
324 write32(gctl, read32(gctl) | 0x1);
325 pci_write_config8(dev, PCI_COMMAND, 0);
326 pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
327}
328
329static int place_device_in_d3hot(device_t dev)
330{
Lee Leahy1072e7d2017-03-16 17:35:32 -0700331 unsigned int offset;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700332
Lee Leahy32471722015-04-20 15:20:28 -0700333 printk(BIOS_SPEW, "%s/%s ( %s )\n",
334 __FILE__, __func__, dev_name(dev));
335
336 /*
337 * Parts of the HDA block are used for LPE audio as well.
338 * Therefore assume the HDA will never be put into D3Hot.
339 */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700340 if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) {
341 hda_work_around(dev);
342 return 0;
343 }
344
345 offset = pci_find_capability(dev, PCI_CAP_ID_PM);
346
347 if (offset != 0) {
348 set_d3hot_bits(dev, offset);
349 return 0;
350 }
351
Lee Leahy32471722015-04-20 15:20:28 -0700352 /*
353 * For some reason some of the devices don't have the capability
354 * pointer set correctly. Work around this by hard coding the offset.
355 */
356#define DEV_CASE(name_) \
357 case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
358
Lee Leahy77ff0b12015-05-05 15:07:29 -0700359 switch (dev->path.pci.devfn) {
Lee Leahy32471722015-04-20 15:20:28 -0700360 DEV_CASE(SDIO) :
361 DEV_CASE(SD) :
362 DEV_CASE(MMC) :
363 DEV_CASE(LPE) :
364 DEV_CASE(SIO_DMA1) :
365 DEV_CASE(I2C1) :
366 DEV_CASE(I2C2) :
367 DEV_CASE(I2C3) :
368 DEV_CASE(I2C4) :
369 DEV_CASE(I2C5) :
370 DEV_CASE(I2C6) :
371 DEV_CASE(I2C7) :
372 DEV_CASE(SIO_DMA2) :
373 DEV_CASE(PWM1) :
374 DEV_CASE(PWM2) :
375 DEV_CASE(HSUART1) :
376 DEV_CASE(HSUART2) :
377 DEV_CASE(SPI) :
Lee Leahy77ff0b12015-05-05 15:07:29 -0700378 offset = 0x80;
379 break;
Lee Leahy32471722015-04-20 15:20:28 -0700380 DEV_CASE(SATA) :
381 DEV_CASE(XHCI) :
Lee Leahy77ff0b12015-05-05 15:07:29 -0700382 offset = 0x70;
383 break;
Lee Leahy32471722015-04-20 15:20:28 -0700384 DEV_CASE(HDA) :
385 DEV_CASE(SMBUS) :
Lee Leahy77ff0b12015-05-05 15:07:29 -0700386 offset = 0x50;
387 break;
Lee Leahy32471722015-04-20 15:20:28 -0700388 DEV_CASE(TXE) :
Lee Leahy77ff0b12015-05-05 15:07:29 -0700389 /* TXE cannot be placed in D3Hot. */
390 return 0;
Lee Leahy32471722015-04-20 15:20:28 -0700391 DEV_CASE(PCIE_PORT1) :
392 DEV_CASE(PCIE_PORT2) :
393 DEV_CASE(PCIE_PORT3) :
394 DEV_CASE(PCIE_PORT4) :
Lee Leahy77ff0b12015-05-05 15:07:29 -0700395 offset = 0xa0;
396 break;
397 }
398
399 if (offset != 0) {
400 set_d3hot_bits(dev, offset);
401 return 0;
402 }
403
404 return -1;
405}
406
407/* Common PCI device function disable. */
408void southcluster_enable_dev(device_t dev)
409{
410 uint32_t reg32;
411
Lee Leahy32471722015-04-20 15:20:28 -0700412 printk(BIOS_SPEW, "%s/%s ( %s )\n",
413 __FILE__, __func__, dev_name(dev));
Lee Leahy77ff0b12015-05-05 15:07:29 -0700414 if (!dev->enabled) {
415 int slot = PCI_SLOT(dev->path.pci.devfn);
416 int func = PCI_FUNC(dev->path.pci.devfn);
417 printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n",
418 dev_path(dev), slot, func);
419
420 /* Ensure memory, io, and bus master are all disabled */
421 reg32 = pci_read_config32(dev, PCI_COMMAND);
422 reg32 &= ~(PCI_COMMAND_MASTER |
423 PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
424 pci_write_config32(dev, PCI_COMMAND, reg32);
425
426 /* Place device in D3Hot */
427 if (place_device_in_d3hot(dev) < 0) {
428 printk(BIOS_WARNING,
429 "Could not place %02x.%01x into D3Hot. "
430 "Keeping device visible.\n", slot, func);
431 return;
432 }
433 /* Disable this device if possible */
434 sc_disable_devfn(dev);
435 } else {
436 /* Enable SERR */
437 reg32 = pci_read_config32(dev, PCI_COMMAND);
438 reg32 |= PCI_COMMAND_SERR;
439 pci_write_config32(dev, PCI_COMMAND, reg32);
440 }
441}
442
443static struct device_operations device_ops = {
444 .read_resources = sc_read_resources,
445 .set_resources = pci_dev_set_resources,
446 .enable_resources = NULL,
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700447 .acpi_inject_dsdt_generator = southcluster_inject_dsdt,
448 .write_acpi_tables = southcluster_write_acpi_tables,
Lee Leahy77ff0b12015-05-05 15:07:29 -0700449 .init = sc_init,
450 .enable = southcluster_enable_dev,
Lee Leahy32471722015-04-20 15:20:28 -0700451 .scan_bus = scan_lpc_bus,
Lee Leahy77ff0b12015-05-05 15:07:29 -0700452 .ops_pci = &soc_pci_ops,
453};
454
455static const struct pci_driver southcluster __pci_driver = {
456 .ops = &device_ops,
457 .vendor = PCI_VENDOR_ID_INTEL,
458 .device = LPC_DEVID,
459};
460
Aaron Durbin64031672018-04-21 14:45:32 -0600461int __weak mainboard_get_spi_config(struct spi_config *cfg)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700462{
Lee Leahy32471722015-04-20 15:20:28 -0700463 printk(BIOS_SPEW, "%s/%s ( 0x%p )\n",
464 __FILE__, __func__, (void *)cfg);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700465 return -1;
466}
467
468static void finalize_chipset(void *unused)
469{
Lee Leahy32471722015-04-20 15:20:28 -0700470 void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
471 void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS);
472 void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
473 void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
474 uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700475 struct spi_config cfg;
476
Lee Leahy32471722015-04-20 15:20:28 -0700477 printk(BIOS_SPEW, "%s/%s ( 0x%p )\n",
478 __FILE__, __func__, unused);
479
Lee Leahy77ff0b12015-05-05 15:07:29 -0700480 /* Set the lock enable on the BIOS control register. */
481 write32(bcr, read32(bcr) | BCR_LE);
482
483 /* Set BIOS lock down bit controlling boot block size and swapping. */
484 write32(gcs, read32(gcs) | BILD);
485
486 /* Lock sleep stretching policy and set SMI lock. */
487 write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK);
488
489 /* Set the CF9 lock. */
490 write32(etr, read32(etr) | CF9LOCK);
491
492 if (mainboard_get_spi_config(&cfg) < 0) {
493 printk(BIOS_DEBUG, "No SPI lockdown configuration.\n");
494 } else {
495 write16(spi + PREOP, cfg.preop);
496 write16(spi + OPTYPE, cfg.optype);
497 write32(spi + OPMENU0, cfg.opmenu[0]);
498 write32(spi + OPMENU1, cfg.opmenu[1]);
499 write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
500 write32(spi + UVSCC, cfg.uvscc);
501 write32(spi + LVSCC, cfg.lvscc | VCL);
502 }
Lee Leahy32471722015-04-20 15:20:28 -0700503 spi_init();
Hannah Williams3fa80a92017-03-22 16:33:36 -0700504 enable_serirq_quiet_mode();
Lee Leahy77ff0b12015-05-05 15:07:29 -0700505
506 printk(BIOS_DEBUG, "Finalizing SMM.\n");
507 outb(APM_CNT_FINALIZE, APM_CNT);
508}
509
Hannah Williams2cfdde72015-04-15 19:48:07 -0700510BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, finalize_chipset, NULL);