commit bd5233eb3dbe2a7e3a0369ef13d4851062c347bd
author Frans Hendriks <fhendriks@eltan.com> Wed Dec 05 15:24:48 2018 +0100
committer Patrick Georgi <pgeorgi@google.com> Thu Dec 06 11:59:52 2018 +0000
tree 9b8689c6732527e3223d739cdbbe56b486903e7e
parent 4f4322dd68575402e099e2dfda057687388f064e

src/soc/intel/braswell/southcluster.c: Config i8254 timer

ISA timer is not configured.
Add call setup_i8254().

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: If45c4975d147f28a456198ea290efba1c8b0464b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/soc/intel/braswell/southcluster.c

diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 0c88004..6ea2ea9 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -4,6 +4,7 @@
  * Copyright (C) 2008-2009 coresystems GmbH
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,6 +26,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/i8254.h>
 #include <romstage_handoff.h>
 #include <soc/acpi.h>
 #include <soc/iomap.h>
@@ -182,6 +184,8 @@
 			read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
 	}
 
+	/* Initialize i8254 timers */
+	setup_i8254();
 }
 
 /*