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review.coreboot.org / coreboot / 0f209b58d2e0d884b4ce9e76e0a769d122e99ac8 / . / src / soc / amd / genoa / Kconfig
blob: 8b138317a80ccf8d47b1a4781473f7b4a7ab35f1 [file] [log] [blame]
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]1config SOC_AMD_GENOA
2 bool
3
4if SOC_AMD_GENOA
5
6config SOC_SPECIFIC_OPTIONS
7 def_bool y
8 select ARCH_X86
9 select HAVE_EXP_X86_64_SUPPORT
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]10 select RESET_VECTOR_IN_RAM
11 select SOC_AMD_COMMON
12 select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Arthur Heymans4da9d6b42023-07-13 14:19:09 +0200[diff] [blame]13 select SOC_AMD_COMMON_BLOCK_AOAC
Varshit Pandya95d78d92023-10-04 19:30:21 +0530[diff] [blame]14 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
Arthur Heymans48167b12023-07-13 14:07:54 +0200[diff] [blame]15 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
Arthur Heymansc666a912023-07-13 14:34:10 +0200[diff] [blame]16 select SOC_AMD_COMMON_BLOCK_HAS_ESPI
Arthur Heymansc5122f92023-07-14 23:27:31 +0200[diff] [blame]17 select SOC_AMD_COMMON_BLOCK_IOMMU
Arthur Heymansc666a912023-07-13 14:34:10 +0200[diff] [blame]18 select SOC_AMD_COMMON_BLOCK_LPC
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]19 select SOC_AMD_COMMON_BLOCK_NONCAR
20 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Felix Held0f209b52023-10-26 14:27:57 +0200[diff] [blame^]21 select SOC_AMD_COMMON_BLOCK_PSP_GEN2
Felix Held51d1f302023-10-04 21:10:36 +0200[diff] [blame]22 select SOC_AMD_COMMON_BLOCK_PSP_SPL
Varshit Pandyac0f19832023-10-04 19:26:21 +0530[diff] [blame]23 select SOC_AMD_COMMON_BLOCK_SMI
Varshit Pandya0a2d2a92023-10-16 17:26:35 +0530[diff] [blame]24 select SOC_AMD_COMMON_BLOCK_SMU
25 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
Arthur Heymans48167b12023-07-13 14:07:54 +0200[diff] [blame]26 select SOC_AMD_COMMON_BLOCK_TSC
Varshit Pandya970d7702023-10-06 18:14:02 +0530[diff] [blame]27 select SOC_AMD_COMMON_BLOCK_UART
Arthur Heymansc666a912023-07-13 14:34:10 +0200[diff] [blame]28 select SOC_AMD_COMMON_BLOCK_USE_ESPI
Arthur Heymanse4eba132023-07-13 14:02:42 +0200[diff] [blame]29 select X86_CUSTOM_BOOTMEDIA
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]30
31config USE_EXP_X86_64_SUPPORT
32 default y
33
vbpandya87d8b8c2023-09-22 20:49:37 +0530[diff] [blame]34config CHIPSET_DEVICETREE
35 string
36 default "soc/amd/genoa/chipset.cb"
37
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]38config EARLY_RESERVED_DRAM_BASE
39 hex
40 default 0x7000000
41 help
42 This variable defines the base address of the DRAM which is reserved
43 for usage by coreboot in early stages (i.e. before ramstage is up).
44 This memory gets reserved in BIOS tables to ensure that the OS does
45 not use it, thus preventing corruption of OS memory in case of S3
46 resume.
47
48config EARLYRAM_BSP_STACK_SIZE
49 hex
50 default 0x1000
51
Varshit Pandyaa7759582023-10-17 21:59:39 +0530[diff] [blame]52config MAX_CPUS
53 int
54 default 384
55
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]56config PSP_APOB_DRAM_ADDRESS
57 hex
58 default 0x7001000
59 help
60 Location in DRAM where the PSP will copy the AGESA PSP Output
61 Block.
62
63config PSP_APOB_DRAM_SIZE
64 hex
65 default 0x20000
66
67config PRERAM_CBMEM_CONSOLE_SIZE
68 hex
69 default 0x1600
70 help
71 Increase this value if preram cbmem console is getting truncated
72
73config C_ENV_BOOTBLOCK_SIZE
74 hex
75 default 0x10000
76 help
77 Sets the size of the bootblock stage that should be loaded in DRAM.
78 This variable controls the DRAM allocation size in linker script
79 for bootblock stage.
80
81config ROMSTAGE_ADDR
82 hex
83 default 0x7040000
84 help
85 Sets the address in DRAM where romstage should be loaded.
86
87config ROMSTAGE_SIZE
88 hex
89 default 0x80000
90 help
91 Sets the size of DRAM allocation for romstage in linker script.
92
Arthur Heymans901f0402023-07-13 14:14:55 +0200[diff] [blame]93config ECAM_MMCONF_BASE_ADDRESS
94 hex
95 default 0xE0000000
96
97config ECAM_MMCONF_BUS_NUMBER
98 int
99 default 256
100
Arthur Heymans8f1c7072023-07-13 12:52:49 +0200[diff] [blame]101menu "PSP Configuration Options"
102
103config AMDFW_CONFIG_FILE
104 string
105 default "src/soc/amd/genoa/fw.cfg"
106
107config PSP_DISABLE_POSTCODES
108 bool "Disable PSP post codes"
109 help
110 Disables the output of port80 post codes from PSP.
111
112config PSP_INIT_ESPI
113 bool "Initialize eSPI in PSP Stage 2 Boot Loader"
114 help
115 Select to initialize the eSPI controller in the PSP Stage 2 Boot
116 Loader.
117
118config PSP_UNLOCK_SECURE_DEBUG
119 bool
120 default y
121
122config HAVE_PSP_WHITELIST_FILE
123 bool "Include a debug whitelist file in PSP build"
124 default n
125 help
126 Support secured unlock prior to reset using a whitelisted
127 serial number. This feature requires a signed whitelist image
128 and bootloader from AMD.
129
130 If unsure, answer 'n'
131
132config PSP_WHITELIST_FILE
133 string "Debug whitelist file path"
134 depends on HAVE_PSP_WHITELIST_FILE
135
Arthur Heymans8f1c7072023-07-13 12:52:49 +0200[diff] [blame]136config PSP_SOFTFUSE_BITS
137 string "PSP Soft Fuse bits to enable"
138 default ""
139 help
140 Space separated list of Soft Fuse bits to enable.
141 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
142 Bit 7: Disable PSP postcodes on Renoir and newer chips only
143 (Set by PSP_DISABLE_PORT80)
144 Bit 15: PSP debug output destination:
145 0=SoC MMIO UART, 1=IO port 0x3F8
146
147 See #57299 (NDA) for additional bit definitions.
148endmenu
149
150
151endif # SOC_AMD_GENOA