Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 66fb5181e38ca04a8eafca1d2abcaec8bfbecde1 / . / src / soc / amd / genoa / Kconfig
blob: cfb878c2ea3a99e973565077dd06ced7a2495c57 [file] [log] [blame]
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]1config SOC_AMD_GENOA
2 bool
3
4if SOC_AMD_GENOA
5
6config SOC_SPECIFIC_OPTIONS
7 def_bool y
8 select ARCH_X86
9 select HAVE_EXP_X86_64_SUPPORT
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]10 select RESET_VECTOR_IN_RAM
11 select SOC_AMD_COMMON
12 select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Arthur Heymans4da9d6b42023-07-13 14:19:09 +0200[diff] [blame]13 select SOC_AMD_COMMON_BLOCK_AOAC
Varshit Pandya95d78d92023-10-04 19:30:21 +0530[diff] [blame]14 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
Arthur Heymans48167b12023-07-13 14:07:54 +0200[diff] [blame]15 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
Arthur Heymansc666a912023-07-13 14:34:10 +0200[diff] [blame]16 select SOC_AMD_COMMON_BLOCK_HAS_ESPI
Arthur Heymansc5122f92023-07-14 23:27:31 +0200[diff] [blame]17 select SOC_AMD_COMMON_BLOCK_IOMMU
Arthur Heymansc666a912023-07-13 14:34:10 +0200[diff] [blame]18 select SOC_AMD_COMMON_BLOCK_LPC
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]19 select SOC_AMD_COMMON_BLOCK_NONCAR
20 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Felix Held51d1f302023-10-04 21:10:36 +0200[diff] [blame]21 select SOC_AMD_COMMON_BLOCK_PSP_SPL
Varshit Pandyac0f19832023-10-04 19:26:21 +0530[diff] [blame]22 select SOC_AMD_COMMON_BLOCK_SMI
Varshit Pandya0a2d2a92023-10-16 17:26:35 +0530[diff] [blame]23 select SOC_AMD_COMMON_BLOCK_SMU
24 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
Arthur Heymans48167b12023-07-13 14:07:54 +0200[diff] [blame]25 select SOC_AMD_COMMON_BLOCK_TSC
Varshit Pandya970d7702023-10-06 18:14:02 +0530[diff] [blame]26 select SOC_AMD_COMMON_BLOCK_UART
Arthur Heymansc666a912023-07-13 14:34:10 +0200[diff] [blame]27 select SOC_AMD_COMMON_BLOCK_USE_ESPI
Arthur Heymanse4eba132023-07-13 14:02:42 +0200[diff] [blame]28 select X86_CUSTOM_BOOTMEDIA
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]29
30config USE_EXP_X86_64_SUPPORT
31 default y
32
vbpandya87d8b8c2023-09-22 20:49:37 +0530[diff] [blame]33config CHIPSET_DEVICETREE
34 string
35 default "soc/amd/genoa/chipset.cb"
36
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]37config EARLY_RESERVED_DRAM_BASE
38 hex
39 default 0x7000000
40 help
41 This variable defines the base address of the DRAM which is reserved
42 for usage by coreboot in early stages (i.e. before ramstage is up).
43 This memory gets reserved in BIOS tables to ensure that the OS does
44 not use it, thus preventing corruption of OS memory in case of S3
45 resume.
46
47config EARLYRAM_BSP_STACK_SIZE
48 hex
49 default 0x1000
50
Varshit Pandyaa7759582023-10-17 21:59:39 +0530[diff] [blame]51config MAX_CPUS
52 int
53 default 384
54
Arthur Heymans6d3682e2023-07-13 12:34:04 +0200[diff] [blame]55config PSP_APOB_DRAM_ADDRESS
56 hex
57 default 0x7001000
58 help
59 Location in DRAM where the PSP will copy the AGESA PSP Output
60 Block.
61
62config PSP_APOB_DRAM_SIZE
63 hex
64 default 0x20000
65
66config PRERAM_CBMEM_CONSOLE_SIZE
67 hex
68 default 0x1600
69 help
70 Increase this value if preram cbmem console is getting truncated
71
72config C_ENV_BOOTBLOCK_SIZE
73 hex
74 default 0x10000
75 help
76 Sets the size of the bootblock stage that should be loaded in DRAM.
77 This variable controls the DRAM allocation size in linker script
78 for bootblock stage.
79
80config ROMSTAGE_ADDR
81 hex
82 default 0x7040000
83 help
84 Sets the address in DRAM where romstage should be loaded.
85
86config ROMSTAGE_SIZE
87 hex
88 default 0x80000
89 help
90 Sets the size of DRAM allocation for romstage in linker script.
91
Arthur Heymans901f0402023-07-13 14:14:55 +0200[diff] [blame]92config ECAM_MMCONF_BASE_ADDRESS
93 hex
94 default 0xE0000000
95
96config ECAM_MMCONF_BUS_NUMBER
97 int
98 default 256
99
Arthur Heymans8f1c7072023-07-13 12:52:49 +0200[diff] [blame]100menu "PSP Configuration Options"
101
102config AMDFW_CONFIG_FILE
103 string
104 default "src/soc/amd/genoa/fw.cfg"
105
106config PSP_DISABLE_POSTCODES
107 bool "Disable PSP post codes"
108 help
109 Disables the output of port80 post codes from PSP.
110
111config PSP_INIT_ESPI
112 bool "Initialize eSPI in PSP Stage 2 Boot Loader"
113 help
114 Select to initialize the eSPI controller in the PSP Stage 2 Boot
115 Loader.
116
117config PSP_UNLOCK_SECURE_DEBUG
118 bool
119 default y
120
121config HAVE_PSP_WHITELIST_FILE
122 bool "Include a debug whitelist file in PSP build"
123 default n
124 help
125 Support secured unlock prior to reset using a whitelisted
126 serial number. This feature requires a signed whitelist image
127 and bootloader from AMD.
128
129 If unsure, answer 'n'
130
131config PSP_WHITELIST_FILE
132 string "Debug whitelist file path"
133 depends on HAVE_PSP_WHITELIST_FILE
134
Arthur Heymans8f1c7072023-07-13 12:52:49 +0200[diff] [blame]135config PSP_SOFTFUSE_BITS
136 string "PSP Soft Fuse bits to enable"
137 default ""
138 help
139 Space separated list of Soft Fuse bits to enable.
140 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
141 Bit 7: Disable PSP postcodes on Renoir and newer chips only
142 (Set by PSP_DISABLE_PORT80)
143 Bit 15: PSP debug output destination:
144 0=SoC MMIO UART, 1=IO port 0x3F8
145
146 See #57299 (NDA) for additional bit definitions.
147endmenu
148
149
150endif # SOC_AMD_GENOA