| Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 1 | config SOC_AMD_GENOA |
| 2 | bool |
| 3 | |
| 4 | if SOC_AMD_GENOA |
| 5 | |
| 6 | config SOC_SPECIFIC_OPTIONS |
| 7 | def_bool y |
| 8 | select ARCH_X86 |
| 9 | select HAVE_EXP_X86_64_SUPPORT |
| 10 | select NO_ECAM_MMCONF_SUPPORT |
| Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 11 | select RESET_VECTOR_IN_RAM |
| 12 | select SOC_AMD_COMMON |
| 13 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| Arthur Heymans | 48167b1 | 2023-07-13 14:07:54 +0200 | [diff] [blame^] | 14 | select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H |
| Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 15 | select SOC_AMD_COMMON_BLOCK_NONCAR |
| 16 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
| Arthur Heymans | 48167b1 | 2023-07-13 14:07:54 +0200 | [diff] [blame^] | 17 | select SOC_AMD_COMMON_BLOCK_TSC |
| Arthur Heymans | e4eba13 | 2023-07-13 14:02:42 +0200 | [diff] [blame] | 18 | select X86_CUSTOM_BOOTMEDIA |
| Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 19 | |
| 20 | config USE_EXP_X86_64_SUPPORT |
| 21 | default y |
| 22 | |
| vbpandya | 87d8b8c | 2023-09-22 20:49:37 +0530 | [diff] [blame] | 23 | config CHIPSET_DEVICETREE |
| 24 | string |
| 25 | default "soc/amd/genoa/chipset.cb" |
| 26 | |
| Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 27 | config EARLY_RESERVED_DRAM_BASE |
| 28 | hex |
| 29 | default 0x7000000 |
| 30 | help |
| 31 | This variable defines the base address of the DRAM which is reserved |
| 32 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 33 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 34 | not use it, thus preventing corruption of OS memory in case of S3 |
| 35 | resume. |
| 36 | |
| 37 | config EARLYRAM_BSP_STACK_SIZE |
| 38 | hex |
| 39 | default 0x1000 |
| 40 | |
| 41 | config PSP_APOB_DRAM_ADDRESS |
| 42 | hex |
| 43 | default 0x7001000 |
| 44 | help |
| 45 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 46 | Block. |
| 47 | |
| 48 | config PSP_APOB_DRAM_SIZE |
| 49 | hex |
| 50 | default 0x20000 |
| 51 | |
| 52 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 53 | hex |
| 54 | default 0x1600 |
| 55 | help |
| 56 | Increase this value if preram cbmem console is getting truncated |
| 57 | |
| 58 | config C_ENV_BOOTBLOCK_SIZE |
| 59 | hex |
| 60 | default 0x10000 |
| 61 | help |
| 62 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 63 | This variable controls the DRAM allocation size in linker script |
| 64 | for bootblock stage. |
| 65 | |
| 66 | config ROMSTAGE_ADDR |
| 67 | hex |
| 68 | default 0x7040000 |
| 69 | help |
| 70 | Sets the address in DRAM where romstage should be loaded. |
| 71 | |
| 72 | config ROMSTAGE_SIZE |
| 73 | hex |
| 74 | default 0x80000 |
| 75 | help |
| 76 | Sets the size of DRAM allocation for romstage in linker script. |
| 77 | |
| Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 78 | menu "PSP Configuration Options" |
| 79 | |
| 80 | config AMDFW_CONFIG_FILE |
| 81 | string |
| 82 | default "src/soc/amd/genoa/fw.cfg" |
| 83 | |
| 84 | config PSP_DISABLE_POSTCODES |
| 85 | bool "Disable PSP post codes" |
| 86 | help |
| 87 | Disables the output of port80 post codes from PSP. |
| 88 | |
| 89 | config PSP_INIT_ESPI |
| 90 | bool "Initialize eSPI in PSP Stage 2 Boot Loader" |
| 91 | help |
| 92 | Select to initialize the eSPI controller in the PSP Stage 2 Boot |
| 93 | Loader. |
| 94 | |
| 95 | config PSP_UNLOCK_SECURE_DEBUG |
| 96 | bool |
| 97 | default y |
| 98 | |
| 99 | config HAVE_PSP_WHITELIST_FILE |
| 100 | bool "Include a debug whitelist file in PSP build" |
| 101 | default n |
| 102 | help |
| 103 | Support secured unlock prior to reset using a whitelisted |
| 104 | serial number. This feature requires a signed whitelist image |
| 105 | and bootloader from AMD. |
| 106 | |
| 107 | If unsure, answer 'n' |
| 108 | |
| 109 | config PSP_WHITELIST_FILE |
| 110 | string "Debug whitelist file path" |
| 111 | depends on HAVE_PSP_WHITELIST_FILE |
| 112 | |
| 113 | config HAVE_SPL_FILE |
| 114 | bool |
| 115 | |
| 116 | config SPL_TABLE_FILE |
| 117 | string "SPL table file" |
| 118 | depends on HAVE_SPL_FILE |
| 119 | default "3rdparty/amd_blobs_internal/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin" |
| 120 | |
| 121 | config PSP_SOFTFUSE_BITS |
| 122 | string "PSP Soft Fuse bits to enable" |
| 123 | default "" |
| 124 | help |
| 125 | Space separated list of Soft Fuse bits to enable. |
| 126 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 127 | Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| 128 | (Set by PSP_DISABLE_PORT80) |
| 129 | Bit 15: PSP debug output destination: |
| 130 | 0=SoC MMIO UART, 1=IO port 0x3F8 |
| 131 | |
| 132 | See #57299 (NDA) for additional bit definitions. |
| 133 | endmenu |
| 134 | |
| 135 | |
| 136 | endif # SOC_AMD_GENOA |