| Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 1 | config SOC_AMD_GENOA |
| 2 | bool |
| 3 | |
| 4 | if SOC_AMD_GENOA |
| 5 | |
| 6 | config SOC_SPECIFIC_OPTIONS |
| 7 | def_bool y |
| 8 | select ARCH_X86 |
| 9 | select HAVE_EXP_X86_64_SUPPORT |
| 10 | select NO_ECAM_MMCONF_SUPPORT |
| 11 | select NO_MONOTONIC_TIMER |
| 12 | select RESET_VECTOR_IN_RAM |
| 13 | select SOC_AMD_COMMON |
| 14 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| 15 | select SOC_AMD_COMMON_BLOCK_NONCAR |
| 16 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
| 17 | select UNKNOWN_TSC_RATE |
| 18 | |
| 19 | config USE_EXP_X86_64_SUPPORT |
| 20 | default y |
| 21 | |
| vbpandya | 87d8b8c | 2023-09-22 20:49:37 +0530 | [diff] [blame^] | 22 | config CHIPSET_DEVICETREE |
| 23 | string |
| 24 | default "soc/amd/genoa/chipset.cb" |
| 25 | |
| Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 26 | config EARLY_RESERVED_DRAM_BASE |
| 27 | hex |
| 28 | default 0x7000000 |
| 29 | help |
| 30 | This variable defines the base address of the DRAM which is reserved |
| 31 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 32 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 33 | not use it, thus preventing corruption of OS memory in case of S3 |
| 34 | resume. |
| 35 | |
| 36 | config EARLYRAM_BSP_STACK_SIZE |
| 37 | hex |
| 38 | default 0x1000 |
| 39 | |
| 40 | config PSP_APOB_DRAM_ADDRESS |
| 41 | hex |
| 42 | default 0x7001000 |
| 43 | help |
| 44 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 45 | Block. |
| 46 | |
| 47 | config PSP_APOB_DRAM_SIZE |
| 48 | hex |
| 49 | default 0x20000 |
| 50 | |
| 51 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 52 | hex |
| 53 | default 0x1600 |
| 54 | help |
| 55 | Increase this value if preram cbmem console is getting truncated |
| 56 | |
| 57 | config C_ENV_BOOTBLOCK_SIZE |
| 58 | hex |
| 59 | default 0x10000 |
| 60 | help |
| 61 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 62 | This variable controls the DRAM allocation size in linker script |
| 63 | for bootblock stage. |
| 64 | |
| 65 | config ROMSTAGE_ADDR |
| 66 | hex |
| 67 | default 0x7040000 |
| 68 | help |
| 69 | Sets the address in DRAM where romstage should be loaded. |
| 70 | |
| 71 | config ROMSTAGE_SIZE |
| 72 | hex |
| 73 | default 0x80000 |
| 74 | help |
| 75 | Sets the size of DRAM allocation for romstage in linker script. |
| 76 | |
| 77 | endif |