soc/amd/genoa: Add timer & tsc support
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76501
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index 7ef5707..b73b53c 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -8,13 +8,13 @@
select ARCH_X86
select HAVE_EXP_X86_64_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
- select NO_MONOTONIC_TIMER
select RESET_VECTOR_IN_RAM
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+ select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
- select UNKNOWN_TSC_RATE
+ select SOC_AMD_COMMON_BLOCK_TSC
select X86_CUSTOM_BOOTMEDIA
config USE_EXP_X86_64_SUPPORT