Blame - src/soc/amd/genoa/Kconfig - coreboot

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Arthur Heymans	6d3682e	2023-07-13 12:34:04 +0200	[diff] [blame]	1	config SOC_AMD_GENOA
				2	bool
				3
				4	if SOC_AMD_GENOA
				5
				6	config SOC_SPECIFIC_OPTIONS
				7	def_bool y
				8	select ARCH_X86
				9	select HAVE_EXP_X86_64_SUPPORT
Arthur Heymans	6d3682e	2023-07-13 12:34:04 +0200	[diff] [blame]	10	select RESET_VECTOR_IN_RAM
				11	select SOC_AMD_COMMON
				12	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Arthur Heymans	48167b1	2023-07-13 14:07:54 +0200	[diff] [blame]	13	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
Arthur Heymans	6d3682e	2023-07-13 12:34:04 +0200	[diff] [blame]	14	select SOC_AMD_COMMON_BLOCK_NONCAR
				15	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Arthur Heymans	48167b1	2023-07-13 14:07:54 +0200	[diff] [blame]	16	select SOC_AMD_COMMON_BLOCK_TSC
Arthur Heymans	e4eba13	2023-07-13 14:02:42 +0200	[diff] [blame]	17	select X86_CUSTOM_BOOTMEDIA
Arthur Heymans	6d3682e	2023-07-13 12:34:04 +0200	[diff] [blame]	18
				19	config USE_EXP_X86_64_SUPPORT
				20	default y
				21
vbpandya	87d8b8c	2023-09-22 20:49:37 +0530	[diff] [blame]	22	config CHIPSET_DEVICETREE
				23	string
				24	default "soc/amd/genoa/chipset.cb"
				25
Arthur Heymans	6d3682e	2023-07-13 12:34:04 +0200	[diff] [blame]	26	config EARLY_RESERVED_DRAM_BASE
				27	hex
				28	default 0x7000000
				29	help
				30	This variable defines the base address of the DRAM which is reserved
				31	for usage by coreboot in early stages (i.e. before ramstage is up).
				32	This memory gets reserved in BIOS tables to ensure that the OS does
				33	not use it, thus preventing corruption of OS memory in case of S3
				34	resume.
				35
				36	config EARLYRAM_BSP_STACK_SIZE
				37	hex
				38	default 0x1000
				39
				40	config PSP_APOB_DRAM_ADDRESS
				41	hex
				42	default 0x7001000
				43	help
				44	Location in DRAM where the PSP will copy the AGESA PSP Output
				45	Block.
				46
				47	config PSP_APOB_DRAM_SIZE
				48	hex
				49	default 0x20000
				50
				51	config PRERAM_CBMEM_CONSOLE_SIZE
				52	hex
				53	default 0x1600
				54	help
				55	Increase this value if preram cbmem console is getting truncated
				56
				57	config C_ENV_BOOTBLOCK_SIZE
				58	hex
				59	default 0x10000
				60	help
				61	Sets the size of the bootblock stage that should be loaded in DRAM.
				62	This variable controls the DRAM allocation size in linker script
				63	for bootblock stage.
				64
				65	config ROMSTAGE_ADDR
				66	hex
				67	default 0x7040000
				68	help
				69	Sets the address in DRAM where romstage should be loaded.
				70
				71	config ROMSTAGE_SIZE
				72	hex
				73	default 0x80000
				74	help
				75	Sets the size of DRAM allocation for romstage in linker script.
				76
Arthur Heymans	901f040	2023-07-13 14:14:55 +0200	[diff] [blame^]	77	config ECAM_MMCONF_BASE_ADDRESS
				78	hex
				79	default 0xE0000000
				80
				81	config ECAM_MMCONF_BUS_NUMBER
				82	int
				83	default 256
				84
Arthur Heymans	8f1c707	2023-07-13 12:52:49 +0200	[diff] [blame]	85	menu "PSP Configuration Options"
				86
				87	config AMDFW_CONFIG_FILE
				88	string
				89	default "src/soc/amd/genoa/fw.cfg"
				90
				91	config PSP_DISABLE_POSTCODES
				92	bool "Disable PSP post codes"
				93	help
				94	Disables the output of port80 post codes from PSP.
				95
				96	config PSP_INIT_ESPI
				97	bool "Initialize eSPI in PSP Stage 2 Boot Loader"
				98	help
				99	Select to initialize the eSPI controller in the PSP Stage 2 Boot
				100	Loader.
				101
				102	config PSP_UNLOCK_SECURE_DEBUG
				103	bool
				104	default y
				105
				106	config HAVE_PSP_WHITELIST_FILE
				107	bool "Include a debug whitelist file in PSP build"
				108	default n
				109	help
				110	Support secured unlock prior to reset using a whitelisted
				111	serial number. This feature requires a signed whitelist image
				112	and bootloader from AMD.
				113
				114	If unsure, answer 'n'
				115
				116	config PSP_WHITELIST_FILE
				117	string "Debug whitelist file path"
				118	depends on HAVE_PSP_WHITELIST_FILE
				119
				120	config HAVE_SPL_FILE
				121	bool
				122
				123	config SPL_TABLE_FILE
				124	string "SPL table file"
				125	depends on HAVE_SPL_FILE
				126	default "3rdparty/amd_blobs_internal/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin"
				127
				128	config PSP_SOFTFUSE_BITS
				129	string "PSP Soft Fuse bits to enable"
				130	default ""
				131	help
				132	Space separated list of Soft Fuse bits to enable.
				133	Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
				134	Bit 7: Disable PSP postcodes on Renoir and newer chips only
				135	(Set by PSP_DISABLE_PORT80)
				136	Bit 15: PSP debug output destination:
				137	0=SoC MMIO UART, 1=IO port 0x3F8
				138
				139	See #57299 (NDA) for additional bit definitions.
				140	endmenu
				141
				142
				143	endif # SOC_AMD_GENOA