src/soc/amd/genoa/Kconfig

config SOC_AMD_GENOA
	bool

if SOC_AMD_GENOA

config SOC_SPECIFIC_OPTIONS
	def_bool y
	select ARCH_X86
	select HAVE_EXP_X86_64_SUPPORT
	select RESET_VECTOR_IN_RAM
	select SOC_AMD_COMMON
	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
	select SOC_AMD_COMMON_BLOCK_AOAC
	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
	select SOC_AMD_COMMON_BLOCK_LPC
	select SOC_AMD_COMMON_BLOCK_NONCAR
	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
	select SOC_AMD_COMMON_BLOCK_SMI
	select SOC_AMD_COMMON_BLOCK_TSC
	select SOC_AMD_COMMON_BLOCK_UART
	select SOC_AMD_COMMON_BLOCK_USE_ESPI
	select X86_CUSTOM_BOOTMEDIA

config USE_EXP_X86_64_SUPPORT
	default y

config CHIPSET_DEVICETREE
	string
	default "soc/amd/genoa/chipset.cb"

config EARLY_RESERVED_DRAM_BASE
	hex
	default 0x7000000
	help
	  This variable defines the base address of the DRAM which is reserved
	  for usage by coreboot in early stages (i.e. before ramstage is up).
	  This memory gets reserved in BIOS tables to ensure that the OS does
	  not use it, thus preventing corruption of OS memory in case of S3
	  resume.

config EARLYRAM_BSP_STACK_SIZE
	hex
	default 0x1000

config PSP_APOB_DRAM_ADDRESS
	hex
	default 0x7001000
	help
	  Location in DRAM where the PSP will copy the AGESA PSP Output
	  Block.

config PSP_APOB_DRAM_SIZE
	hex
	default 0x20000

config PRERAM_CBMEM_CONSOLE_SIZE
	hex
	default 0x1600
	help
	  Increase this value if preram cbmem console is getting truncated

config C_ENV_BOOTBLOCK_SIZE
	hex
	default 0x10000
	help
	  Sets the size of the bootblock stage that should be loaded in DRAM.
	  This variable controls the DRAM allocation size in linker script
	  for bootblock stage.

config ROMSTAGE_ADDR
	hex
	default 0x7040000
	help
	  Sets the address in DRAM where romstage should be loaded.

config ROMSTAGE_SIZE
	hex
	default 0x80000
	help
	  Sets the size of DRAM allocation for romstage in linker script.

config ECAM_MMCONF_BASE_ADDRESS
	hex
	default 0xE0000000

config ECAM_MMCONF_BUS_NUMBER
	int
	default 256

menu "PSP Configuration Options"

config AMDFW_CONFIG_FILE
	string
	default "src/soc/amd/genoa/fw.cfg"

config PSP_DISABLE_POSTCODES
	bool "Disable PSP post codes"
	help
	  Disables the output of port80 post codes from PSP.

config PSP_INIT_ESPI
	bool "Initialize eSPI in PSP Stage 2 Boot Loader"
	help
	  Select to initialize the eSPI controller in the PSP Stage 2 Boot
	  Loader.

config	PSP_UNLOCK_SECURE_DEBUG
	bool
	default y

config HAVE_PSP_WHITELIST_FILE
	bool "Include a debug whitelist file in PSP build"
	default n
	help
	  Support secured unlock prior to reset using a whitelisted
	  serial number. This feature requires a signed whitelist image
	  and bootloader from AMD.

	  If unsure, answer 'n'

config PSP_WHITELIST_FILE
	string "Debug whitelist file path"
	depends on HAVE_PSP_WHITELIST_FILE

config PERFORM_SPL_FUSING
	bool "Send SPL fuse command to PSP"
	default n
	help
	  Send the Security Patch Level (SPL) fusing command to the PSP in
	  order to update the minimum SPL version to be written to the SoC's
	  fuse bits. This will prevent using any embedded firmware components
	  with lower SPL version.

	  If unsure, answer 'n'

config SPL_TABLE_FILE
	string "SPL table file override"
	help
	  Provide a mainboard-specific Security Patch Level (SPL) table file
	  override. The SPL file is required to support PSP FW anti-rollback
	  and needs to be created by AMD. The default SPL file specified in the
	  SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule
	  and applies to all boards that use the SoC without verstage on PSP.
	  In the verstage on PSP case, a different SPL file is specific as an
	  override via this Kconfig option.

config PSP_SOFTFUSE_BITS
	string "PSP Soft Fuse bits to enable"
	default ""
	help
	  Space separated list of Soft Fuse bits to enable.
	  Bit 0:  Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
	  Bit 7:  Disable PSP postcodes on Renoir and newer chips only
	          (Set by PSP_DISABLE_PORT80)
	  Bit 15: PSP debug output destination:
	          0=SoC MMIO UART, 1=IO port 0x3F8

	  See #57299 (NDA) for additional bit definitions.
endmenu


endif # SOC_AMD_GENOA