blob: 9a0d7924315cf9d0c9e9155edbe25088fe6acff7 [file] [log] [blame]
Stefan Reinauer5c554632012-04-04 00:09:50 +02001config CPU_INTEL_MODEL_206AX
2 bool
3
Nico Huber772a1542019-05-10 16:48:14 +02004if CPU_INTEL_MODEL_206AX
Stefan Reinauer5c554632012-04-04 00:09:50 +02005
Patrick Rudolphb50b6a52020-08-20 16:50:01 +02006config ARCH_EXP_X86_64
7 bool "Experimental 64bit support"
8 depends on USE_NATIVE_RAMINIT
9 default n
10
Stefan Reinauer5c554632012-04-04 00:09:50 +020011config CPU_SPECIFIC_OPTIONS
12 def_bool y
Patrick Rudolphb50b6a52020-08-20 16:50:01 +020013 select ARCH_ALL_STAGES_X86_32 if !ARCH_EXP_X86_64
14 select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64
Angel Pons8e035e32021-06-22 12:58:20 +020015 select ARCH_X86
Shelley Chen6c2568f2020-09-25 09:30:44 -070016 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
Arthur Heymans7e6946a2019-01-21 17:55:02 +010017 select MMX
Stefan Reinauer5c554632012-04-04 00:09:50 +020018 select SSE2
Patrick Rudolphb9959e22017-06-06 10:44:29 +020019 select UDELAY_TSC
Patrick Rudolphb9959e22017-06-06 10:44:29 +020020 select TSC_MONOTONIC_TIMER
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060021 select SUPPORT_CPU_UCODE_IN_CBFS
Sven Schnelle51676b12012-07-29 19:18:03 +020022 #select AP_IN_SIPI_WAIT
Stefan Reinauer0db68202012-08-07 14:44:51 -070023 select TSC_SYNC_MFENCE
Matt DeVilliered6fe2f2016-12-14 16:12:43 -060024 select CPU_INTEL_COMMON
Kyösti Mälkkic00e2fb2019-02-11 11:36:17 +020025 select CPU_INTEL_COMMON_TIMEBASE
Stefan Reinauer5c554632012-04-04 00:09:50 +020026
Stefan Reinauer5c554632012-04-04 00:09:50 +020027config SMM_TSEG_SIZE
28 hex
29 default 0x800000
30
Arthur Heymans67031a52018-02-05 19:08:03 +010031config SMM_RESERVED_SIZE
32 hex
33 default 0x100000
34
35# Intel Enhanced Debug region must be 4MB
36config IED_REGION_SIZE
37 hex
38 default 0x400000
39
Angel Ponsd71754d2020-05-29 00:42:15 +020040config MAX_CPUS
41 int
42 default 8
43
Vadim Bendebury999e94c2012-06-19 04:20:20 +000044endif