| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 1 | config CPU_INTEL_MODEL_206AX |
| 2 | bool |
| 3 | |
| 4 | config CPU_INTEL_MODEL_306AX |
| 5 | bool |
| 6 | |
| 7 | if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX |
| 8 | |
| 9 | config CPU_SPECIFIC_OPTIONS |
| 10 | def_bool y |
| Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 11 | select ARCH_BOOTBLOCK_X86_32 |
| Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 12 | select ARCH_VERSTAGE_X86_32 |
| Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_RAMSTAGE_X86_32 |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 15 | select SMP |
| 16 | select SSE2 |
| Patrick Rudolph | b9959e2 | 2017-06-06 10:44:29 +0200 | [diff] [blame^] | 17 | select UDELAY_TSC |
| 18 | select TSC_CONSTANT_RATE |
| 19 | select TSC_MONOTONIC_TIMER |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 20 | select SMM_TSEG |
| Alexandru Gagniuc | 66e0c4c | 2013-12-04 22:21:15 -0600 | [diff] [blame] | 21 | select SUPPORT_CPU_UCODE_IN_CBFS |
| Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 22 | #select AP_IN_SIPI_WAIT |
| Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 23 | select TSC_SYNC_MFENCE |
| Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 24 | select CPU_INTEL_COMMON |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 25 | |
| 26 | config BOOTBLOCK_CPU_INIT |
| 27 | string |
| 28 | default "cpu/intel/model_206ax/bootblock.c" |
| 29 | |
| Kyösti Mälkki | c13d65c | 2016-11-18 19:03:29 +0200 | [diff] [blame] | 30 | config XIP_ROM_SIZE |
| 31 | hex |
| 32 | default 0x20000 if USE_NATIVE_RAMINIT |
| 33 | |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 34 | config SMM_TSEG_SIZE |
| 35 | hex |
| 36 | default 0x800000 |
| 37 | |
| Vadim Bendebury | 999e94c | 2012-06-19 04:20:20 +0000 | [diff] [blame] | 38 | endif |