blob: dbb8982121524f4b397e98c4d9f474819046f32b [file] [log] [blame]
Stefan Reinauer5c554632012-04-04 00:09:50 +02001config CPU_INTEL_MODEL_206AX
2 bool
3
Nico Huber772a1542019-05-10 16:48:14 +02004if CPU_INTEL_MODEL_206AX
Stefan Reinauer5c554632012-04-04 00:09:50 +02005
6config CPU_SPECIFIC_OPTIONS
7 def_bool y
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07008 select ARCH_BOOTBLOCK_X86_32
Stefan Reinauer77b16552015-01-14 19:51:47 +01009 select ARCH_VERSTAGE_X86_32
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070010 select ARCH_ROMSTAGE_X86_32
11 select ARCH_RAMSTAGE_X86_32
Stefan Reinauer5c554632012-04-04 00:09:50 +020012 select SMP
Arthur Heymans7e6946a2019-01-21 17:55:02 +010013 select MMX
Stefan Reinauer5c554632012-04-04 00:09:50 +020014 select SSE2
Patrick Rudolphb9959e22017-06-06 10:44:29 +020015 select UDELAY_TSC
16 select TSC_CONSTANT_RATE
17 select TSC_MONOTONIC_TIMER
Stefan Reinauer5c554632012-04-04 00:09:50 +020018 select SMM_TSEG
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060019 select SUPPORT_CPU_UCODE_IN_CBFS
Sven Schnelle51676b12012-07-29 19:18:03 +020020 #select AP_IN_SIPI_WAIT
Stefan Reinauer0db68202012-08-07 14:44:51 -070021 select TSC_SYNC_MFENCE
Matt DeVilliered6fe2f2016-12-14 16:12:43 -060022 select CPU_INTEL_COMMON
Arthur Heymans67031a52018-02-05 19:08:03 +010023 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Arthur Heymansedbf5d92018-01-25 20:03:42 +010024 select PARALLEL_MP
Arthur Heymans74f9fe62019-04-24 12:29:44 +020025 select NO_FIXED_XIP_ROM_SIZE
Stefan Reinauer5c554632012-04-04 00:09:50 +020026
27config BOOTBLOCK_CPU_INIT
28 string
29 default "cpu/intel/model_206ax/bootblock.c"
30
Stefan Reinauer5c554632012-04-04 00:09:50 +020031config SMM_TSEG_SIZE
32 hex
33 default 0x800000
34
Arthur Heymans67031a52018-02-05 19:08:03 +010035config SMM_RESERVED_SIZE
36 hex
37 default 0x100000
38
39# Intel Enhanced Debug region must be 4MB
40config IED_REGION_SIZE
41 hex
42 default 0x400000
43
Vadim Bendebury999e94c2012-06-19 04:20:20 +000044endif