blob: c6a50207c5d07e10269898145102fa6bac9e8af5 [file] [log] [blame]
Stefan Reinauer5c554632012-04-04 00:09:50 +02001config CPU_INTEL_MODEL_206AX
2 bool
3
Nico Huber772a1542019-05-10 16:48:14 +02004if CPU_INTEL_MODEL_206AX
Stefan Reinauer5c554632012-04-04 00:09:50 +02005
6config CPU_SPECIFIC_OPTIONS
7 def_bool y
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07008 select ARCH_BOOTBLOCK_X86_32
Stefan Reinauer77b16552015-01-14 19:51:47 +01009 select ARCH_VERSTAGE_X86_32
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070010 select ARCH_ROMSTAGE_X86_32
11 select ARCH_RAMSTAGE_X86_32
Stefan Reinauer5c554632012-04-04 00:09:50 +020012 select SMP
Arthur Heymans7e6946a2019-01-21 17:55:02 +010013 select MMX
Stefan Reinauer5c554632012-04-04 00:09:50 +020014 select SSE2
Patrick Rudolphb9959e22017-06-06 10:44:29 +020015 select UDELAY_TSC
Patrick Rudolphb9959e22017-06-06 10:44:29 +020016 select TSC_MONOTONIC_TIMER
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060017 select SUPPORT_CPU_UCODE_IN_CBFS
Sven Schnelle51676b12012-07-29 19:18:03 +020018 #select AP_IN_SIPI_WAIT
Stefan Reinauer0db68202012-08-07 14:44:51 -070019 select TSC_SYNC_MFENCE
Matt DeVilliered6fe2f2016-12-14 16:12:43 -060020 select CPU_INTEL_COMMON
Kyösti Mälkkic00e2fb2019-02-11 11:36:17 +020021 select CPU_INTEL_COMMON_TIMEBASE
Arthur Heymansedbf5d92018-01-25 20:03:42 +010022 select PARALLEL_MP
Stefan Reinauer5c554632012-04-04 00:09:50 +020023
Stefan Reinauer5c554632012-04-04 00:09:50 +020024config SMM_TSEG_SIZE
25 hex
26 default 0x800000
27
Arthur Heymans67031a52018-02-05 19:08:03 +010028config SMM_RESERVED_SIZE
29 hex
30 default 0x100000
31
32# Intel Enhanced Debug region must be 4MB
33config IED_REGION_SIZE
34 hex
35 default 0x400000
36
Angel Ponsd71754d2020-05-29 00:42:15 +020037config MAX_CPUS
38 int
39 default 8
40
Vadim Bendebury999e94c2012-06-19 04:20:20 +000041endif