blob: 7f73da9ab4ef3bcca1e580c31351183d91a825b9 [file] [log] [blame]
Stefan Reinauer5c554632012-04-04 00:09:50 +02001config CPU_INTEL_MODEL_206AX
2 bool
3
4config CPU_INTEL_MODEL_306AX
5 bool
6
7if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX
8
9config CPU_SPECIFIC_OPTIONS
10 def_bool y
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070011 select ARCH_BOOTBLOCK_X86_32
Stefan Reinauer77b16552015-01-14 19:51:47 +010012 select ARCH_VERSTAGE_X86_32
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070013 select ARCH_ROMSTAGE_X86_32
14 select ARCH_RAMSTAGE_X86_32
Stefan Reinauer5c554632012-04-04 00:09:50 +020015 select SMP
Arthur Heymans7e6946a2019-01-21 17:55:02 +010016 select MMX
Stefan Reinauer5c554632012-04-04 00:09:50 +020017 select SSE2
Patrick Rudolphb9959e22017-06-06 10:44:29 +020018 select UDELAY_TSC
19 select TSC_CONSTANT_RATE
20 select TSC_MONOTONIC_TIMER
Stefan Reinauer5c554632012-04-04 00:09:50 +020021 select SMM_TSEG
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060022 select SUPPORT_CPU_UCODE_IN_CBFS
Sven Schnelle51676b12012-07-29 19:18:03 +020023 #select AP_IN_SIPI_WAIT
Stefan Reinauer0db68202012-08-07 14:44:51 -070024 select TSC_SYNC_MFENCE
Matt DeVilliered6fe2f2016-12-14 16:12:43 -060025 select CPU_INTEL_COMMON
Arthur Heymans67031a52018-02-05 19:08:03 +010026 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Arthur Heymansedbf5d92018-01-25 20:03:42 +010027 select PARALLEL_MP
Stefan Reinauer5c554632012-04-04 00:09:50 +020028
29config BOOTBLOCK_CPU_INIT
30 string
31 default "cpu/intel/model_206ax/bootblock.c"
32
Kyösti Mälkkic13d65c2016-11-18 19:03:29 +020033config XIP_ROM_SIZE
34 hex
35 default 0x20000 if USE_NATIVE_RAMINIT
36
Stefan Reinauer5c554632012-04-04 00:09:50 +020037config SMM_TSEG_SIZE
38 hex
39 default 0x800000
40
Arthur Heymans67031a52018-02-05 19:08:03 +010041config SMM_RESERVED_SIZE
42 hex
43 default 0x100000
44
45# Intel Enhanced Debug region must be 4MB
46config IED_REGION_SIZE
47 hex
48 default 0x400000
49
Vadim Bendebury999e94c2012-06-19 04:20:20 +000050endif