blob: 109b6b53b3362a9adc477bafaeeebf9bbcefcf66 [file] [log] [blame]
Stefan Reinauer5c554632012-04-04 00:09:50 +02001config CPU_INTEL_MODEL_206AX
2 bool
3
Nico Huber772a1542019-05-10 16:48:14 +02004if CPU_INTEL_MODEL_206AX
Stefan Reinauer5c554632012-04-04 00:09:50 +02005
Patrick Rudolphb50b6a52020-08-20 16:50:01 +02006config ARCH_EXP_X86_64
7 bool "Experimental 64bit support"
8 depends on USE_NATIVE_RAMINIT
9 default n
10
Stefan Reinauer5c554632012-04-04 00:09:50 +020011config CPU_SPECIFIC_OPTIONS
12 def_bool y
Patrick Rudolphb50b6a52020-08-20 16:50:01 +020013 select ARCH_ALL_STAGES_X86_32 if !ARCH_EXP_X86_64
14 select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64
Shelley Chen6c2568f2020-09-25 09:30:44 -070015 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
Arthur Heymans7e6946a2019-01-21 17:55:02 +010016 select MMX
Stefan Reinauer5c554632012-04-04 00:09:50 +020017 select SSE2
Patrick Rudolphb9959e22017-06-06 10:44:29 +020018 select UDELAY_TSC
Patrick Rudolphb9959e22017-06-06 10:44:29 +020019 select TSC_MONOTONIC_TIMER
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060020 select SUPPORT_CPU_UCODE_IN_CBFS
Sven Schnelle51676b12012-07-29 19:18:03 +020021 #select AP_IN_SIPI_WAIT
Stefan Reinauer0db68202012-08-07 14:44:51 -070022 select TSC_SYNC_MFENCE
Matt DeVilliered6fe2f2016-12-14 16:12:43 -060023 select CPU_INTEL_COMMON
Kyösti Mälkkic00e2fb2019-02-11 11:36:17 +020024 select CPU_INTEL_COMMON_TIMEBASE
Stefan Reinauer5c554632012-04-04 00:09:50 +020025
Stefan Reinauer5c554632012-04-04 00:09:50 +020026config SMM_TSEG_SIZE
27 hex
28 default 0x800000
29
Arthur Heymans67031a52018-02-05 19:08:03 +010030config SMM_RESERVED_SIZE
31 hex
32 default 0x100000
33
34# Intel Enhanced Debug region must be 4MB
35config IED_REGION_SIZE
36 hex
37 default 0x400000
38
Angel Ponsd71754d2020-05-29 00:42:15 +020039config MAX_CPUS
40 int
41 default 8
42
Vadim Bendebury999e94c2012-06-19 04:20:20 +000043endif