Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | config SOC_INTEL_BRASWELL |
| 2 | bool |
| 3 | help |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 4 | Braswell M/D part support. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 5 | |
| 6 | if SOC_INTEL_BRASWELL |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 11 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 12 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 15 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 16 | select CACHE_MRC_SETTINGS |
Kyösti Mälkki | 730df3c | 2016-06-18 07:39:31 +0300 | [diff] [blame] | 17 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | select COLLECT_TIMESTAMPS |
Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 19 | select SUPPORT_CPU_UCODE_IN_CBFS |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 20 | select MICROCODE_BLOB_NOT_IN_BLOB_REPO |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 22 | select HAVE_MONOTONIC_TIMER |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 23 | select HAVE_SMI_HANDLER |
Aaron Durbin | f5ff854 | 2016-05-05 10:38:03 -0500 | [diff] [blame] | 24 | select NO_FIXED_XIP_ROM_SIZE |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 25 | select PARALLEL_MP |
| 26 | select PCIEXP_ASPM |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 27 | select PCIEXP_CLK_PM |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 28 | select PCIEXP_COMMON_CLOCK |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 29 | select PLATFORM_USES_FSP1_1 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | select REG_SCRIPT |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 31 | select RTC |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 32 | select SOC_INTEL_COMMON |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 33 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Frans Hendriks | 59ae2ef | 2019-02-28 15:16:00 +0100 | [diff] [blame] | 34 | select SOC_INTEL_COMMON_BLOCK |
| 35 | select SOC_INTEL_COMMON_BLOCK_HDA |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 36 | select SOC_INTEL_COMMON_RESET |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 37 | select SMP |
| 38 | select SPI_FLASH |
| 39 | select SSE2 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 40 | select TSC_CONSTANT_RATE |
| 41 | select TSC_MONOTONIC_TIMER |
| 42 | select TSC_SYNC_MFENCE |
| 43 | select UDELAY_TSC |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 44 | select USE_GENERIC_FSP_CAR_INC |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 45 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Martin Roth | 3a54318 | 2015-09-28 15:27:24 -0600 | [diff] [blame] | 46 | select HAVE_SPI_CONSOLE_SUPPORT |
Nico Huber | 2e7f6cc | 2017-05-22 15:58:03 +0200 | [diff] [blame] | 47 | select HAVE_FSP_GOP |
Matt DeVillier | 51ee7ce | 2017-08-20 18:21:10 -0500 | [diff] [blame] | 48 | select GENERIC_GPIO_LIB |
Patrick Rudolph | c7edf18 | 2017-09-26 19:34:35 +0200 | [diff] [blame] | 49 | select INTEL_GMA_ACPI |
| 50 | select INTEL_GMA_SWSMISCI |
Matt DeVillier | d3d0f07 | 2018-11-10 17:44:36 -0600 | [diff] [blame] | 51 | select CPU_INTEL_COMMON |
Frans Hendriks | b27fb33 | 2019-03-04 08:02:43 +0100 | [diff] [blame] | 52 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 53 | select C_ENVIRONMENT_BOOTBLOCK |
| 54 | |
| 55 | config DCACHE_BSP_STACK_SIZE |
| 56 | hex |
| 57 | default 0x2000 |
| 58 | help |
| 59 | The amount of anticipated stack usage in CAR by bootblock and |
| 60 | other stages. |
| 61 | |
| 62 | config C_ENV_BOOTBLOCK_SIZE |
| 63 | hex |
| 64 | default 0x8000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 65 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 66 | config VBOOT |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 67 | select VBOOT_MUST_REQUEST_DISPLAY |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 68 | select VBOOT_STARTS_IN_ROMSTAGE |
| 69 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 70 | config MMCONF_BASE_ADDRESS |
Arthur Heymans | 9c27eda | 2017-06-13 14:47:28 +0200 | [diff] [blame] | 71 | hex |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 72 | default 0xe0000000 |
| 73 | |
| 74 | config MAX_CPUS |
| 75 | int |
| 76 | default 4 |
| 77 | |
| 78 | config CPU_ADDR_BITS |
| 79 | int |
| 80 | default 36 |
| 81 | |
| 82 | config SMM_TSEG_SIZE |
| 83 | hex |
| 84 | default 0x800000 |
| 85 | |
| 86 | config SMM_RESERVED_SIZE |
| 87 | hex |
| 88 | default 0x100000 |
| 89 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 90 | # Cache As RAM region layout: |
| 91 | # |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 92 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
Kyösti Mälkki | 2bad1e7 | 2016-07-26 14:03:31 +0300 | [diff] [blame] | 93 | # | Stack | |
| 94 | # | | | |
| 95 | # | v | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 96 | # +-------------+ |
| 97 | # | ^ | |
| 98 | # | | | |
| 99 | # | CAR Globals | |
| 100 | # +-------------+ DCACHE_RAM_BASE |
| 101 | # |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 102 | |
| 103 | config DCACHE_RAM_BASE |
Arthur Heymans | 9c27eda | 2017-06-13 14:47:28 +0200 | [diff] [blame] | 104 | hex |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 105 | default 0xfef00000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 106 | |
| 107 | config DCACHE_RAM_SIZE |
Arthur Heymans | 9c27eda | 2017-06-13 14:47:28 +0200 | [diff] [blame] | 108 | hex |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 109 | default 0x4000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 110 | help |
| 111 | The size of the cache-as-ram region required during bootblock |
| 112 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 113 | must add up to a power of 2. |
| 114 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 115 | config RESET_ON_INVALID_RAMSTAGE_CACHE |
| 116 | bool "Reset the system on S3 wake when ramstage cache invalid." |
| 117 | default n |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 118 | help |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 119 | The haswell romstage code caches the loaded ramstage program |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 120 | in SMM space. On S3 wake the romstage will copy over a fresh |
| 121 | ramstage that was cached in the SMM space. This option determines |
| 122 | the action to take when the ramstage cache is invalid. If selected |
| 123 | the system will reset otherwise the ramstage will be reloaded from |
| 124 | cbfs. |
| 125 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 126 | config ENABLE_BUILTIN_COM1 |
| 127 | bool "Enable builtin COM1 Serial Port" |
| 128 | default n |
| 129 | help |
| 130 | The PMC has a legacy COM1 serial port. Choose this option to |
| 131 | configure the pads and enable it. This serial port can be used for |
| 132 | the debug console. |
| 133 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 134 | config IED_REGION_SIZE |
| 135 | hex |
| 136 | default 0x400000 |
| 137 | |
Frans Hendriks | f2af702 | 2018-11-16 12:08:41 +0100 | [diff] [blame] | 138 | config DISABLE_HPET |
| 139 | bool "Disable the HPET device" |
| 140 | default n |
| 141 | help |
| 142 | Enable this to disable the HPET support |
| 143 | Solves the Linux MP-BIOS bug timer not connected. |
| 144 | |
Matt DeVillier | fd7440d | 2019-04-23 12:21:17 -0500 | [diff] [blame] | 145 | config USE_GOOGLE_FSP |
| 146 | bool |
| 147 | help |
| 148 | Select this to use Google's custom Braswell FSP header/binary |
| 149 | instead of the public release on Github. Only google/cyan |
| 150 | variants require this; all other boards should use the public release. |
| 151 | |
| 152 | config FSP_HEADER_PATH |
| 153 | string |
| 154 | default "$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP |
| 155 | default "3rdparty/fsp/BraswellFspBinPkg/Include/" |
| 156 | help |
| 157 | Location of FSP header file FspUpdVpd.h |
| 158 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 159 | endif |