Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | config SOC_INTEL_BRASWELL |
| 2 | bool |
| 3 | help |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 4 | Braswell M/D part support. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 5 | |
| 6 | if SOC_INTEL_BRASWELL |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 11 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 12 | select ARCH_ROMSTAGE_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 14 | select BACKUP_DEFAULT_SMM_REGION |
| 15 | select CACHE_MRC_SETTINGS |
Alexandru Gagniuc | 27fea06 | 2015-08-29 20:00:24 -0700 | [diff] [blame] | 16 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | select COLLECT_TIMESTAMPS |
Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 18 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 19 | select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 20 | select HAS_PRECBMEM_TIMESTAMP_REGION |
| 21 | select HAVE_MONOTONIC_TIMER |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | select HAVE_SMI_HANDLER |
| 23 | select HAVE_HARD_RESET |
| 24 | select MMCONF_SUPPORT |
| 25 | select MMCONF_SUPPORT_DEFAULT |
| 26 | select RELOCATABLE_MODULES |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 27 | select PARALLEL_MP |
| 28 | select PCIEXP_ASPM |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 29 | select PCIEXP_CLK_PM |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | select PCIEXP_COMMON_CLOCK |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 31 | select PCIEXP_L1_SUB_STATE |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 32 | select PLATFORM_USES_FSP1_1 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | select REG_SCRIPT |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 34 | select SOC_INTEL_COMMON |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 35 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 36 | select SOC_INTEL_COMMON_FSP_RAM_INIT |
| 37 | select SOC_INTEL_COMMON_FSP_ROMSTAGE |
| 38 | select SOC_INTEL_COMMON_RESET |
| 39 | select SOC_INTEL_COMMON_STACK |
| 40 | select SOC_INTEL_COMMON_STAGE_CACHE |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 41 | select SMM_TSEG |
| 42 | select SMP |
| 43 | select SPI_FLASH |
| 44 | select SSE2 |
| 45 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 46 | select TSC_CONSTANT_RATE |
| 47 | select TSC_MONOTONIC_TIMER |
| 48 | select TSC_SYNC_MFENCE |
| 49 | select UDELAY_TSC |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 50 | select USE_GENERIC_FSP_CAR_INC |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 51 | select HAVE_INTEL_FIRMWARE |
Martin Roth | 3a54318 | 2015-09-28 15:27:24 -0600 | [diff] [blame^] | 52 | select HAVE_SPI_CONSOLE_SUPPORT |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 53 | |
| 54 | config BOOTBLOCK_CPU_INIT |
| 55 | string |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 56 | default "soc/intel/braswell/bootblock/bootblock.c" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 57 | |
| 58 | config MMCONF_BASE_ADDRESS |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 59 | hex "PCIe CFG Base Address" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 60 | default 0xe0000000 |
| 61 | |
| 62 | config MAX_CPUS |
| 63 | int |
| 64 | default 4 |
| 65 | |
| 66 | config CPU_ADDR_BITS |
| 67 | int |
| 68 | default 36 |
| 69 | |
| 70 | config SMM_TSEG_SIZE |
| 71 | hex |
| 72 | default 0x800000 |
| 73 | |
| 74 | config SMM_RESERVED_SIZE |
| 75 | hex |
| 76 | default 0x100000 |
| 77 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 78 | # Cache As RAM region layout: |
| 79 | # |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 80 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 81 | # | Stack |\ |
| 82 | # | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 83 | # | v |/ |
| 84 | # +-------------+ |
| 85 | # | ^ | |
| 86 | # | | | |
| 87 | # | CAR Globals | |
| 88 | # +-------------+ DCACHE_RAM_BASE |
| 89 | # |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 90 | |
| 91 | config DCACHE_RAM_BASE |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 92 | hex "Temporary RAM Base Address" |
| 93 | default 0xfef00000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 94 | |
| 95 | config DCACHE_RAM_SIZE |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 96 | hex "Temporary RAM Size" |
| 97 | default 0x4000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 98 | help |
| 99 | The size of the cache-as-ram region required during bootblock |
| 100 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 101 | must add up to a power of 2. |
| 102 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 103 | config DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 104 | hex |
| 105 | default 0x800 |
| 106 | help |
| 107 | The amount of anticipated stack usage from the data cache |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 108 | during pre-ram rom stage execution. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 109 | |
| 110 | config RESET_ON_INVALID_RAMSTAGE_CACHE |
| 111 | bool "Reset the system on S3 wake when ramstage cache invalid." |
| 112 | default n |
| 113 | depends on RELOCATABLE_RAMSTAGE |
| 114 | help |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 115 | The haswell romstage code caches the loaded ramstage program |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 116 | in SMM space. On S3 wake the romstage will copy over a fresh |
| 117 | ramstage that was cached in the SMM space. This option determines |
| 118 | the action to take when the ramstage cache is invalid. If selected |
| 119 | the system will reset otherwise the ramstage will be reloaded from |
| 120 | cbfs. |
| 121 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 122 | config ENABLE_BUILTIN_COM1 |
| 123 | bool "Enable builtin COM1 Serial Port" |
| 124 | default n |
| 125 | help |
| 126 | The PMC has a legacy COM1 serial port. Choose this option to |
| 127 | configure the pads and enable it. This serial port can be used for |
| 128 | the debug console. |
| 129 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 130 | config HAVE_IFD_BIN |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 131 | def_bool y |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 132 | |
| 133 | config BUILD_WITH_FAKE_IFD |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 134 | def_bool !HAVE_IFD_BIN |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 135 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 136 | config HAVE_ME_BIN |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 137 | def_bool y |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 138 | |
| 139 | config IED_REGION_SIZE |
| 140 | hex |
| 141 | default 0x400000 |
| 142 | |
Aaron Durbin | 3953e39 | 2015-09-03 00:41:29 -0500 | [diff] [blame] | 143 | config CHIPSET_BOOTBLOCK_INCLUDE |
| 144 | string |
| 145 | default "soc/intel/braswell/bootblock/timestamp.inc" |
| 146 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 147 | endif |