src/mainboard/google/glados/devicetree.cb

chip soc/intel/skylake

	# IGD Displays
	register "gfx" = "GMA_STATIC_DISPLAYS(0)"

	register "panel_cfg" = "{
		.up_delay_ms		=  200,
		.down_delay_ms		=   50,
		.cycle_delay_ms		=  500,
		.backlight_on_delay_ms	=    1,
		.backlight_off_delay_ms	=  200,
		.backlight_pwm_hz	= 1000,
	}"

	# Enable deep Sx states
	register "deep_s3_enable_ac" = "0"
	register "deep_s3_enable_dc" = "0"
	register "deep_s5_enable_ac" = "1"
	register "deep_s5_enable_dc" = "1"
	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "GPP_B"
	register "gpe0_dw1" = "GPP_D"
	register "gpe0_dw2" = "GPP_E"

	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
	register "gen1_dec" = "0x00fc0801"
	register "gen2_dec" = "0x000c0201"

	# Enable DPTF
	register "dptf_enable" = "1"

	# FSP Configuration
	register "SataSalpSupport" = "0"
	register "SataPortsEnable[0]" = "0"
	register "DspEnable" = "1"
	register "IoBufferOwnership" = "3"
	register "ScsEmmcHs400Enabled" = "1"
	register "SkipExtGfxScan" = "1"
	register "SaGv" = "SaGv_Enabled"
	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
	register "PmConfigSlpS4MinAssert" = "4"        # 4s
	register "PmConfigSlpSusMinAssert" = "3"       # 4s
	register "PmConfigSlpAMinAssert" = "3"         # 2s

	# Enable Root port 1
	register "PcieRpEnable[0]" = "1"
	# Enable CLKREQ#
	register "PcieRpClkReqSupport[0]" = "1"
	# RP 1 uses SRCCLKREQ1#
	register "PcieRpClkReqNumber[0]" = "1"

	# Must leave UART0 enabled or SD/eMMC will not work as PCI
	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
		[PchSerialIoIndexUart0] = PchSerialIoPci,
		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
	}"

	# I2C4 is 1.8V
	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"

	# PL2 override 25W
	register "power_limits_config" = "{
		.tdp_pl2_override = 25,
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

	device domain 0 on
		device ref igpu		on  end
		device ref sa_thermal	on  end
		device ref south_xhci	on  end
		device ref thermal	on  end
		device ref i2c0		on  end
		device ref i2c1		on  end
		device ref heci1	on  end
		device ref uart2	on  end
		device ref i2c4		on  end
		device ref pcie_rp1	on
			chip drivers/wifi/generic
				register "wake" = "GPE0_DW0_16"
				device pci 00.0 on end
			end
		end
		device ref uart0	on  end
		device ref emmc		on  end
		device ref lpc_espi	on
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end
		device ref hda		on  end
		device ref smbus	on  end
		device ref fast_spi	on  end
	end
end