Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Matt DeVillier | 338c8d4 | 2018-07-16 20:29:10 -0500 | [diff] [blame^] | 3 | # IGD Displays |
| 4 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 5 | |
Nico Huber | 55c5777 | 2018-12-16 03:39:35 +0100 | [diff] [blame] | 6 | register "gpu_pp_up_delay_ms" = "200" |
| 7 | register "gpu_pp_down_delay_ms" = " 50" |
| 8 | register "gpu_pp_cycle_delay_ms" = "500" |
| 9 | register "gpu_pp_backlight_on_delay_ms" = " 1" |
| 10 | register "gpu_pp_backlight_off_delay_ms" = "200" |
| 11 | |
| 12 | register "gpu_pch_backlight_pwm_hz" = "1000" |
| 13 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 14 | # Enable deep Sx states |
| 15 | register "deep_s3_enable_ac" = "0" |
| 16 | register "deep_s3_enable_dc" = "0" |
| 17 | register "deep_s5_enable_ac" = "1" |
| 18 | register "deep_s5_enable_dc" = "1" |
| 19 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 20 | |
| 21 | # GPE configuration |
| 22 | # Note that GPE events called out in ASL code rely on this |
| 23 | # route. i.e. If this route changes then the affected GPE |
| 24 | # offset bits also need to be changed. |
| 25 | register "gpe0_dw0" = "GPP_B" |
| 26 | register "gpe0_dw1" = "GPP_D" |
| 27 | register "gpe0_dw2" = "GPP_E" |
| 28 | |
| 29 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 30 | register "gen1_dec" = "0x00fc0801" |
| 31 | register "gen2_dec" = "0x000c0201" |
| 32 | |
| 33 | # Enable "Intel Speed Shift Technology" |
| 34 | register "speed_shift_enable" = "1" |
| 35 | |
| 36 | # Enable DPTF |
| 37 | register "dptf_enable" = "1" |
| 38 | |
| 39 | # FSP Configuration |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 40 | register "ProbelessTrace" = "0" |
| 41 | register "EnableLan" = "0" |
| 42 | register "EnableSata" = "0" |
| 43 | register "SataSalpSupport" = "0" |
| 44 | register "SataMode" = "0" |
| 45 | register "SataPortsEnable[0]" = "0" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 46 | register "EnableAzalia" = "1" |
| 47 | register "DspEnable" = "1" |
| 48 | register "IoBufferOwnership" = "3" |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 49 | register "EnableTraceHub" = "0" |
| 50 | register "SsicPortEnable" = "0" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 51 | register "SmbusEnable" = "1" |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 52 | register "Cio2Enable" = "0" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 53 | register "ScsEmmcEnabled" = "1" |
| 54 | register "ScsEmmcHs400Enabled" = "1" |
| 55 | register "ScsSdCardEnabled" = "0" |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 56 | register "PttSwitch" = "0" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 57 | register "SkipExtGfxScan" = "1" |
| 58 | register "Device4Enable" = "1" |
| 59 | register "HeciEnabled" = "0" |
| 60 | register "SaGv" = "3" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 61 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 62 | register "PmConfigSlpS4MinAssert" = "4" # 4s |
| 63 | register "PmConfigSlpSusMinAssert" = "3" # 4s |
| 64 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 65 | register "PmTimerDisabled" = "1" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 66 | |
| 67 | register "pirqa_routing" = "PCH_IRQ11" |
| 68 | register "pirqb_routing" = "PCH_IRQ10" |
| 69 | register "pirqc_routing" = "PCH_IRQ11" |
| 70 | register "pirqd_routing" = "PCH_IRQ11" |
| 71 | register "pirqe_routing" = "PCH_IRQ11" |
| 72 | register "pirqf_routing" = "PCH_IRQ11" |
| 73 | register "pirqg_routing" = "PCH_IRQ11" |
| 74 | register "pirqh_routing" = "PCH_IRQ11" |
| 75 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 76 | # Enable Root port 1 |
| 77 | register "PcieRpEnable[0]" = "1" |
| 78 | # Enable CLKREQ# |
| 79 | register "PcieRpClkReqSupport[0]" = "1" |
| 80 | # RP 1 uses SRCCLKREQ1# |
| 81 | register "PcieRpClkReqNumber[0]" = "1" |
| 82 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 83 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 84 | register "SerialIoDevMode" = "{ |
| 85 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 86 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 87 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 88 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 89 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 90 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 91 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 92 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 93 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 94 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 95 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 96 | }" |
| 97 | |
Matt DeVillier | d957d12 | 2020-03-31 12:18:44 -0500 | [diff] [blame] | 98 | # I2C4 is 1.8V |
| 99 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" |
| 100 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 101 | # PL2 override 25W |
| 102 | register "tdp_pl2_override" = "25" |
| 103 | |
| 104 | # Send an extra VR mailbox command for the PS4 exit issue |
| 105 | register "SendVrMbxCmd" = "2" |
| 106 | |
| 107 | # Lock Down |
| 108 | register "common_soc_config" = "{ |
| 109 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 110 | }" |
| 111 | |
| 112 | device cpu_cluster 0 on |
| 113 | device lapic 0 on end |
| 114 | end |
| 115 | device domain 0 on |
| 116 | device pci 00.0 on end # Host Bridge |
| 117 | device pci 02.0 on end # Integrated Graphics Device |
| 118 | device pci 14.0 on end # USB xHCI |
| 119 | device pci 14.1 off end # USB xDCI (OTG) |
| 120 | device pci 14.2 on end # Thermal Subsystem |
Matt DeVillier | 0d58e64 | 2020-03-31 13:12:22 -0500 | [diff] [blame] | 121 | device pci 15.0 on end # I2C #0 |
| 122 | device pci 15.1 on end # I2C #1 |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 123 | device pci 15.2 off end # I2C #2 |
| 124 | device pci 15.3 off end # I2C #3 |
| 125 | device pci 16.0 on end # Management Engine Interface 1 |
| 126 | device pci 16.1 off end # Management Engine Interface 2 |
| 127 | device pci 16.2 off end # Management Engine IDE-R |
| 128 | device pci 16.3 off end # Management Engine KT Redirection |
| 129 | device pci 16.4 off end # Management Engine Interface 3 |
| 130 | device pci 17.0 off end # SATA |
| 131 | device pci 19.0 on end # UART #2 |
| 132 | device pci 19.1 off end # I2C #5 |
Matt DeVillier | 0d58e64 | 2020-03-31 13:12:22 -0500 | [diff] [blame] | 133 | device pci 19.2 on end # I2C #4 |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 134 | device pci 1c.0 on |
| 135 | chip drivers/intel/wifi |
| 136 | register "wake" = "GPE0_DW0_16" |
| 137 | device pci 00.0 on end |
| 138 | end |
| 139 | end # PCI Express Port 1 |
| 140 | device pci 1c.1 off end # PCI Express Port 2 |
| 141 | device pci 1c.2 off end # PCI Express Port 3 |
| 142 | device pci 1c.3 off end # PCI Express Port 4 |
| 143 | device pci 1c.4 off end # PCI Express Port 5 |
| 144 | device pci 1c.5 off end # PCI Express Port 6 |
| 145 | device pci 1c.6 off end # PCI Express Port 7 |
| 146 | device pci 1c.7 off end # PCI Express Port 8 |
| 147 | device pci 1d.0 off end # PCI Express Port 9 |
| 148 | device pci 1d.1 off end # PCI Express Port 10 |
| 149 | device pci 1d.2 off end # PCI Express Port 11 |
| 150 | device pci 1d.3 off end # PCI Express Port 12 |
| 151 | device pci 1e.0 on end # UART #0 |
| 152 | device pci 1e.1 off end # UART #1 |
| 153 | device pci 1e.2 off end # GSPI #0 |
| 154 | device pci 1e.3 off end # GSPI #1 |
| 155 | device pci 1e.4 on end # eMMC |
| 156 | device pci 1e.5 off end # SDIO |
| 157 | device pci 1e.6 off end # SDCard |
| 158 | device pci 1f.0 on |
| 159 | chip drivers/pc80/tpm |
| 160 | device pnp 0c31.0 on end |
| 161 | end |
| 162 | chip ec/google/chromeec |
| 163 | device pnp 0c09.0 on end |
| 164 | end |
| 165 | end # LPC Interface |
| 166 | device pci 1f.1 on end # P2SB |
| 167 | device pci 1f.2 on end # Power Management Controller |
Matt DeVillier | 0d58e64 | 2020-03-31 13:12:22 -0500 | [diff] [blame] | 168 | device pci 1f.3 on end # Intel HDA |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 169 | device pci 1f.4 on end # SMBus |
| 170 | device pci 1f.5 on end # PCH SPI |
| 171 | device pci 1f.6 off end # GbE |
| 172 | end |
| 173 | end |