Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Nico Huber | 55c5777 | 2018-12-16 03:39:35 +0100 | [diff] [blame^] | 3 | register "gpu_pp_up_delay_ms" = "200" |
| 4 | register "gpu_pp_down_delay_ms" = " 50" |
| 5 | register "gpu_pp_cycle_delay_ms" = "500" |
| 6 | register "gpu_pp_backlight_on_delay_ms" = " 1" |
| 7 | register "gpu_pp_backlight_off_delay_ms" = "200" |
| 8 | |
| 9 | register "gpu_pch_backlight_pwm_hz" = "1000" |
| 10 | |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 11 | # Enable deep Sx states |
| 12 | register "deep_s3_enable_ac" = "0" |
| 13 | register "deep_s3_enable_dc" = "0" |
| 14 | register "deep_s5_enable_ac" = "1" |
| 15 | register "deep_s5_enable_dc" = "1" |
| 16 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 17 | |
| 18 | # GPE configuration |
| 19 | # Note that GPE events called out in ASL code rely on this |
| 20 | # route. i.e. If this route changes then the affected GPE |
| 21 | # offset bits also need to be changed. |
| 22 | register "gpe0_dw0" = "GPP_B" |
| 23 | register "gpe0_dw1" = "GPP_D" |
| 24 | register "gpe0_dw2" = "GPP_E" |
| 25 | |
| 26 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 27 | register "gen1_dec" = "0x00fc0801" |
| 28 | register "gen2_dec" = "0x000c0201" |
| 29 | |
| 30 | # Enable "Intel Speed Shift Technology" |
| 31 | register "speed_shift_enable" = "1" |
| 32 | |
| 33 | # Enable DPTF |
| 34 | register "dptf_enable" = "1" |
| 35 | |
| 36 | # FSP Configuration |
| 37 | register "EnableAzalia" = "1" |
| 38 | register "DspEnable" = "1" |
| 39 | register "IoBufferOwnership" = "3" |
| 40 | register "SmbusEnable" = "1" |
| 41 | register "ScsEmmcEnabled" = "1" |
| 42 | register "ScsEmmcHs400Enabled" = "1" |
| 43 | register "ScsSdCardEnabled" = "0" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 44 | register "SkipExtGfxScan" = "1" |
| 45 | register "Device4Enable" = "1" |
| 46 | register "HeciEnabled" = "0" |
| 47 | register "SaGv" = "3" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 48 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 49 | register "PmConfigSlpS4MinAssert" = "4" # 4s |
| 50 | register "PmConfigSlpSusMinAssert" = "3" # 4s |
| 51 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 52 | register "PmTimerDisabled" = "1" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 53 | |
| 54 | register "pirqa_routing" = "PCH_IRQ11" |
| 55 | register "pirqb_routing" = "PCH_IRQ10" |
| 56 | register "pirqc_routing" = "PCH_IRQ11" |
| 57 | register "pirqd_routing" = "PCH_IRQ11" |
| 58 | register "pirqe_routing" = "PCH_IRQ11" |
| 59 | register "pirqf_routing" = "PCH_IRQ11" |
| 60 | register "pirqg_routing" = "PCH_IRQ11" |
| 61 | register "pirqh_routing" = "PCH_IRQ11" |
| 62 | |
| 63 | # VR Settings Configuration for 5 Domains |
| 64 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 65 | #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | |
| 66 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 67 | #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | |
| 68 | #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | |
| 69 | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | |
| 70 | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | |
| 71 | #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | |
| 72 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | |
| 73 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | |
| 74 | #| IccMax | 7A | 34A | 34A | 35A | 35A | |
| 75 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | |
| 76 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 77 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 78 | .vr_config_enable = 1, |
| 79 | .psi1threshold = VR_CFG_AMP(20), |
| 80 | .psi2threshold = VR_CFG_AMP(4), |
| 81 | .psi3threshold = VR_CFG_AMP(1), |
| 82 | .psi3enable = 1, |
| 83 | .psi4enable = 1, |
| 84 | .imon_slope = 0x0, |
| 85 | .imon_offset = 0x0, |
| 86 | .icc_max = VR_CFG_AMP(7), |
| 87 | .voltage_limit = 1520, |
| 88 | }" |
| 89 | |
| 90 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 91 | .vr_config_enable = 1, |
| 92 | .psi1threshold = VR_CFG_AMP(20), |
| 93 | .psi2threshold = VR_CFG_AMP(5), |
| 94 | .psi3threshold = VR_CFG_AMP(1), |
| 95 | .psi3enable = 1, |
| 96 | .psi4enable = 1, |
| 97 | .imon_slope = 0x0, |
| 98 | .imon_offset = 0x0, |
| 99 | .icc_max = VR_CFG_AMP(34), |
| 100 | .voltage_limit = 1520, |
| 101 | }" |
| 102 | |
| 103 | register "domain_vr_config[VR_RING]" = "{ |
| 104 | .vr_config_enable = 1, |
| 105 | .psi1threshold = VR_CFG_AMP(20), |
| 106 | .psi2threshold = VR_CFG_AMP(5), |
| 107 | .psi3threshold = VR_CFG_AMP(1), |
| 108 | .psi3enable = 1, |
| 109 | .psi4enable = 1, |
| 110 | .imon_slope = 0x0, |
| 111 | .imon_offset = 0x0, |
| 112 | .icc_max = VR_CFG_AMP(34), |
| 113 | .voltage_limit = 1520, |
| 114 | }" |
| 115 | |
| 116 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 117 | .vr_config_enable = 1, |
| 118 | .psi1threshold = VR_CFG_AMP(20), |
| 119 | .psi2threshold = VR_CFG_AMP(5), |
| 120 | .psi3threshold = VR_CFG_AMP(1), |
| 121 | .psi3enable = 1, |
| 122 | .psi4enable = 1, |
| 123 | .imon_slope = 0x0, |
| 124 | .imon_offset = 0x0, |
| 125 | .icc_max = VR_CFG_AMP(35), |
| 126 | .voltage_limit = 1520, |
| 127 | }" |
| 128 | |
| 129 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 130 | .vr_config_enable = 1, |
| 131 | .psi1threshold = VR_CFG_AMP(20), |
| 132 | .psi2threshold = VR_CFG_AMP(5), |
| 133 | .psi3threshold = VR_CFG_AMP(1), |
| 134 | .psi3enable = 1, |
| 135 | .psi4enable = 1, |
| 136 | .imon_slope = 0x0, |
| 137 | .imon_offset = 0x0, |
| 138 | .icc_max = VR_CFG_AMP(35), |
| 139 | .voltage_limit = 1520, |
| 140 | }" |
| 141 | |
| 142 | # Enable Root port 1 |
| 143 | register "PcieRpEnable[0]" = "1" |
| 144 | # Enable CLKREQ# |
| 145 | register "PcieRpClkReqSupport[0]" = "1" |
| 146 | # RP 1 uses SRCCLKREQ1# |
| 147 | register "PcieRpClkReqNumber[0]" = "1" |
| 148 | |
| 149 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 |
| 150 | register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Card Reader |
| 151 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 152 | register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (board) |
| 153 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| 154 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # PIC MCU |
| 155 | register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) |
| 156 | |
| 157 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 158 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader |
| 159 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board) |
| 160 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) |
| 161 | |
| 162 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V |
| 163 | |
| 164 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 165 | register "SerialIoDevMode" = "{ |
| 166 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 167 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 168 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 169 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 170 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 171 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 172 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 173 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 174 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 175 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 176 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 177 | }" |
| 178 | |
| 179 | # PL2 override 25W |
| 180 | register "tdp_pl2_override" = "25" |
| 181 | |
| 182 | # Send an extra VR mailbox command for the PS4 exit issue |
| 183 | register "SendVrMbxCmd" = "2" |
| 184 | |
| 185 | # Lock Down |
| 186 | register "common_soc_config" = "{ |
| 187 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 188 | }" |
| 189 | |
| 190 | device cpu_cluster 0 on |
| 191 | device lapic 0 on end |
| 192 | end |
| 193 | device domain 0 on |
| 194 | device pci 00.0 on end # Host Bridge |
| 195 | device pci 02.0 on end # Integrated Graphics Device |
| 196 | device pci 14.0 on end # USB xHCI |
| 197 | device pci 14.1 off end # USB xDCI (OTG) |
| 198 | device pci 14.2 on end # Thermal Subsystem |
| 199 | device pci 15.0 on |
| 200 | chip drivers/i2c/generic |
| 201 | register "hid" = ""ELAN0001"" |
| 202 | register "desc" = ""ELAN Touchscreen"" |
| 203 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" |
| 204 | device i2c 10 on end |
| 205 | end |
| 206 | end # I2C #0 |
| 207 | device pci 15.1 on |
| 208 | chip drivers/i2c/generic |
| 209 | register "hid" = ""ELAN0000"" |
| 210 | register "desc" = ""ELAN Touchpad"" |
Matt DeVillier | 6b27c38 | 2018-07-16 20:18:41 -0500 | [diff] [blame] | 211 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" |
Matt DeVillier | bba1ee0 | 2018-07-09 00:58:59 -0500 | [diff] [blame] | 212 | register "wake" = "GPE0_DW0_05" |
| 213 | device i2c 15 on end |
| 214 | end |
| 215 | end # I2C #1 |
| 216 | device pci 15.2 off end # I2C #2 |
| 217 | device pci 15.3 off end # I2C #3 |
| 218 | device pci 16.0 on end # Management Engine Interface 1 |
| 219 | device pci 16.1 off end # Management Engine Interface 2 |
| 220 | device pci 16.2 off end # Management Engine IDE-R |
| 221 | device pci 16.3 off end # Management Engine KT Redirection |
| 222 | device pci 16.4 off end # Management Engine Interface 3 |
| 223 | device pci 17.0 off end # SATA |
| 224 | device pci 19.0 on end # UART #2 |
| 225 | device pci 19.1 off end # I2C #5 |
| 226 | device pci 19.2 on |
| 227 | chip drivers/i2c/nau8825 |
| 228 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" |
| 229 | register "jkdet_enable" = "1" |
| 230 | register "jkdet_pull_enable" = "0" # R389 |
| 231 | register "jkdet_polarity" = "1" # ActiveLow |
| 232 | register "vref_impedance" = "2" # 125kOhm |
| 233 | register "micbias_voltage" = "6" # 2.754 |
| 234 | register "sar_threshold_num" = "4" |
| 235 | register "sar_threshold[0]" = "0x08" |
| 236 | register "sar_threshold[1]" = "0x12" |
| 237 | register "sar_threshold[2]" = "0x26" |
| 238 | register "sar_threshold[3]" = "0x73" |
| 239 | register "sar_hysteresis" = "0" |
| 240 | register "sar_voltage" = "6" |
| 241 | register "sar_compare_time" = "1" # 1us |
| 242 | register "sar_sampling_time" = "1" # 4us |
| 243 | register "short_key_debounce" = "3" # 30ms |
| 244 | register "jack_insert_debounce" = "7" # 512ms |
| 245 | register "jack_eject_debounce" = "0" |
| 246 | device i2c 1a on end |
| 247 | end |
| 248 | end # I2C #4 |
| 249 | device pci 1c.0 on |
| 250 | chip drivers/intel/wifi |
| 251 | register "wake" = "GPE0_DW0_16" |
| 252 | device pci 00.0 on end |
| 253 | end |
| 254 | end # PCI Express Port 1 |
| 255 | device pci 1c.1 off end # PCI Express Port 2 |
| 256 | device pci 1c.2 off end # PCI Express Port 3 |
| 257 | device pci 1c.3 off end # PCI Express Port 4 |
| 258 | device pci 1c.4 off end # PCI Express Port 5 |
| 259 | device pci 1c.5 off end # PCI Express Port 6 |
| 260 | device pci 1c.6 off end # PCI Express Port 7 |
| 261 | device pci 1c.7 off end # PCI Express Port 8 |
| 262 | device pci 1d.0 off end # PCI Express Port 9 |
| 263 | device pci 1d.1 off end # PCI Express Port 10 |
| 264 | device pci 1d.2 off end # PCI Express Port 11 |
| 265 | device pci 1d.3 off end # PCI Express Port 12 |
| 266 | device pci 1e.0 on end # UART #0 |
| 267 | device pci 1e.1 off end # UART #1 |
| 268 | device pci 1e.2 off end # GSPI #0 |
| 269 | device pci 1e.3 off end # GSPI #1 |
| 270 | device pci 1e.4 on end # eMMC |
| 271 | device pci 1e.5 off end # SDIO |
| 272 | device pci 1e.6 off end # SDCard |
| 273 | device pci 1f.0 on |
| 274 | chip drivers/pc80/tpm |
| 275 | device pnp 0c31.0 on end |
| 276 | end |
| 277 | chip ec/google/chromeec |
| 278 | device pnp 0c09.0 on end |
| 279 | end |
| 280 | end # LPC Interface |
| 281 | device pci 1f.1 on end # P2SB |
| 282 | device pci 1f.2 on end # Power Management Controller |
| 283 | device pci 1f.3 on |
| 284 | chip drivers/generic/max98357a |
| 285 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" |
| 286 | register "sdmode_delay" = "5" |
| 287 | device generic 0 on end |
| 288 | end |
| 289 | end # Intel HDA |
| 290 | device pci 1f.4 on end # SMBus |
| 291 | device pci 1f.5 on end # PCH SPI |
| 292 | device pci 1f.6 off end # GbE |
| 293 | end |
| 294 | end |