Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 2 | |
Marshall Dawson | 9db8a44 | 2017-09-20 10:24:28 -0600 | [diff] [blame] | 3 | #include <bootstate.h> |
| 4 | #include <console/console.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 5 | #include <cpu/amd/mtrr.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
Justin TerAvest | 13101a7 | 2018-01-24 14:23:12 -0700 | [diff] [blame] | 8 | #include <drivers/i2c/designware/dw_i2c.h> |
Duncan Laurie | 32bdffa | 2018-05-07 15:37:28 -0700 | [diff] [blame] | 9 | #include <soc/acpi.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 10 | #include <soc/cpu.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 11 | #include <soc/northbridge.h> |
Justin TerAvest | 949d666 | 2018-01-24 14:20:03 -0700 | [diff] [blame] | 12 | #include <soc/pci_devs.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 13 | #include <soc/southbridge.h> |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 14 | #include <amdblocks/psp.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 15 | #include <amdblocks/agesawrapper.h> |
| 16 | #include <amdblocks/agesawrapper_call.h> |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 17 | #include <amdblocks/i2c.h> |
Martin Roth | 8180427 | 2022-11-20 20:30:18 -0700 | [diff] [blame^] | 18 | #include <amdblocks/post_codes.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 19 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 20 | #include "chip.h" |
| 21 | |
Felix Held | a11b472 | 2022-10-13 16:32:23 +0200 | [diff] [blame] | 22 | struct device_operations stoneyridge_cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 23 | .read_resources = noop_read_resources, |
| 24 | .set_resources = noop_set_resources, |
Kyösti Mälkki | 79e12ab | 2020-05-31 09:21:07 +0300 | [diff] [blame] | 25 | .init = mp_cpu_bus_init, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 26 | .acpi_fill_ssdt = generate_cpu_entries, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 27 | }; |
| 28 | |
Duncan Laurie | 32bdffa | 2018-05-07 15:37:28 -0700 | [diff] [blame] | 29 | const char *soc_acpi_name(const struct device *dev) |
Justin TerAvest | 949d666 | 2018-01-24 14:20:03 -0700 | [diff] [blame] | 30 | { |
| 31 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 32 | return "PCI0"; |
Duncan Laurie | 32bdffa | 2018-05-07 15:37:28 -0700 | [diff] [blame] | 33 | |
| 34 | if (dev->path.type == DEVICE_PATH_USB) { |
| 35 | switch (dev->path.usb.port_type) { |
| 36 | case 0: |
| 37 | /* Root Hub */ |
| 38 | return "RHUB"; |
| 39 | case 2: |
| 40 | /* USB2 ports */ |
| 41 | switch (dev->path.usb.port_id) { |
| 42 | case 0: return "HS01"; |
| 43 | case 1: return "HS02"; |
| 44 | case 2: return "HS03"; |
| 45 | case 3: return "HS04"; |
| 46 | case 4: return "HS05"; |
| 47 | case 5: return "HS06"; |
| 48 | case 6: return "HS07"; |
| 49 | case 7: return "HS08"; |
| 50 | } |
| 51 | break; |
| 52 | case 3: |
| 53 | /* USB3 ports */ |
| 54 | switch (dev->path.usb.port_id) { |
| 55 | case 0: return "SS01"; |
| 56 | case 1: return "SS02"; |
| 57 | case 2: return "SS03"; |
| 58 | } |
| 59 | break; |
| 60 | } |
| 61 | return NULL; |
| 62 | } |
| 63 | |
Justin TerAvest | 949d666 | 2018-01-24 14:20:03 -0700 | [diff] [blame] | 64 | if (dev->path.type != DEVICE_PATH_PCI) |
| 65 | return NULL; |
| 66 | |
| 67 | switch (dev->path.pci.devfn) { |
Marc Jones | 6dcb6c2 | 2018-07-26 17:07:13 -0600 | [diff] [blame] | 68 | case GFX_DEVFN: |
| 69 | return "IGFX"; |
Marc Jones | 9022b9d | 2018-05-25 20:53:44 -0600 | [diff] [blame] | 70 | case PCIE0_DEVFN: |
| 71 | return "PBR4"; |
| 72 | case PCIE1_DEVFN: |
| 73 | return "PBR5"; |
| 74 | case PCIE2_DEVFN: |
| 75 | return "PBR6"; |
| 76 | case PCIE3_DEVFN: |
| 77 | return "PBR7"; |
| 78 | case PCIE4_DEVFN: |
| 79 | return "PBR8"; |
Justin TerAvest | 949d666 | 2018-01-24 14:20:03 -0700 | [diff] [blame] | 80 | case EHCI1_DEVFN: |
| 81 | return "EHC0"; |
Justin TerAvest | 949d666 | 2018-01-24 14:20:03 -0700 | [diff] [blame] | 82 | case SD_DEVFN: |
| 83 | return "SDCN"; |
Justin TerAvest | 949d666 | 2018-01-24 14:20:03 -0700 | [diff] [blame] | 84 | case XHCI_DEVFN: |
| 85 | return "XHC0"; |
| 86 | default: |
| 87 | return NULL; |
| 88 | } |
| 89 | }; |
| 90 | |
Felix Held | a11b472 | 2022-10-13 16:32:23 +0200 | [diff] [blame] | 91 | struct device_operations stoneyridge_pci_domain_ops = { |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 92 | .read_resources = domain_read_resources, |
| 93 | .set_resources = pci_domain_set_resources, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 94 | .enable_resources = domain_enable_resources, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 95 | .scan_bus = pci_domain_scan_bus, |
Justin TerAvest | 949d666 | 2018-01-24 14:20:03 -0700 | [diff] [blame] | 96 | .acpi_name = soc_acpi_name, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 97 | }; |
| 98 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 99 | static void soc_init(void *chip_info) |
| 100 | { |
Felix Held | a21690b | 2021-01-29 16:01:10 +0100 | [diff] [blame] | 101 | fch_init(chip_info); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | static void soc_final(void *chip_info) |
| 105 | { |
Felix Held | a21690b | 2021-01-29 16:01:10 +0100 | [diff] [blame] | 106 | fch_final(chip_info); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 107 | fam15_finalize(chip_info); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | struct chip_operations soc_amd_stoneyridge_ops = { |
| 111 | CHIP_NAME("AMD StoneyRidge SOC") |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 112 | .init = soc_init, |
| 113 | .final = soc_final |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 114 | }; |
Marshall Dawson | 9db8a44 | 2017-09-20 10:24:28 -0600 | [diff] [blame] | 115 | |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 116 | static void earliest_ramstage(void *unused) |
Marshall Dawson | 9db8a44 | 2017-09-20 10:24:28 -0600 | [diff] [blame] | 117 | { |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 118 | if (!acpi_is_wakeup_s3()) { |
Martin Roth | 8180427 | 2022-11-20 20:30:18 -0700 | [diff] [blame^] | 119 | post_code(POST_PSP_LOAD_SMU); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 120 | if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) |
Marshall Dawson | 737e56a | 2020-01-19 16:32:08 -0700 | [diff] [blame] | 121 | psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 122 | |
Martin Roth | 8180427 | 2022-11-20 20:30:18 -0700 | [diff] [blame^] | 123 | post_code(POST_AGESA_AMDINITENV); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 124 | do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 125 | } else { |
| 126 | /* Complete the initial system restoration */ |
Martin Roth | 8180427 | 2022-11-20 20:30:18 -0700 | [diff] [blame^] | 127 | post_code(POST_AGESA_AMDS3LATERESTORE); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 128 | do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 129 | } |
Marshall Dawson | 9db8a44 | 2017-09-20 10:24:28 -0600 | [diff] [blame] | 130 | } |
| 131 | |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 132 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL); |