amd/stoneyridge: Convert MP init to mp_init_with_smm
Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build
mp_ops with the necessary callbacks. Note also that this patch removes
cpu_bus_scan. Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time. A later patch will add TSEG SMM
capabilities for the APU.
This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.
Signed-off-by: Marshall Dawson <firstname.lastname@example.org>
Tested-by: build bot (Jenkins) <email@example.com>
Reviewed-by: Kyösti Mälkki <firstname.lastname@example.org>
Reviewed-by: Aaron Durbin <email@example.com>
9 files changed