soc/amd/stoneyridge: Add I2C devicetree support.
This commit establishes the stoneyridge implementation for i2c entries
in the devicetree.cb file.
BUG=b:72121803
Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index d447ffa..d3a8bc4 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -20,6 +20,7 @@
#include <cpu/cpu.h>
#include <device/device.h>
#include <device/pci.h>
+#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
@@ -28,6 +29,10 @@
#include <amdblocks/agesawrapper.h>
#include <amdblocks/agesawrapper_call.h>
+/* Supplied by i2c.c */
+extern struct device_operations stoneyridge_i2c_mmio_ops;
+extern const char *i2c_acpi_name(const struct device *dev);
+
struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
@@ -79,6 +84,9 @@
dev->ops = &cpu_bus_ops;
else if (dev->path.type == DEVICE_PATH_PCI)
sb_enable(dev);
+ else if (dev->path.type == DEVICE_PATH_MMIO)
+ if (i2c_acpi_name(dev) != NULL)
+ dev->ops = &stoneyridge_i2c_mmio_ops;
}
static void soc_init(void *chip_info)