Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 2 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 3 | #include <commonlib/clamp.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <console/usb.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 6 | #include <delay.h> |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <device/pci_def.h> |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 10 | #include <northbridge/intel/sandybridge/chip.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 11 | #include <stdbool.h> |
| 12 | #include <stdint.h> |
| 13 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 14 | #include "raminit_native.h" |
| 15 | #include "raminit_common.h" |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 16 | #include "raminit_tables.h" |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 17 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 18 | #define SNB_MIN_DCLK_133_MULT 3 |
| 19 | #define SNB_MAX_DCLK_133_MULT 8 |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 20 | #define IVB_MIN_DCLK_133_MULT 3 |
| 21 | #define IVB_MAX_DCLK_133_MULT 10 |
| 22 | #define IVB_MIN_DCLK_100_MULT 7 |
| 23 | #define IVB_MAX_DCLK_100_MULT 12 |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 24 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 25 | /* Frequency multiplier */ |
| 26 | static u32 get_FRQ(const ramctr_timing *ctrl) |
| 27 | { |
| 28 | const u32 FRQ = 256000 / (ctrl->tCK * ctrl->base_freq); |
| 29 | |
| 30 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 31 | if (ctrl->base_freq == 100) |
| 32 | return clamp_u32(IVB_MIN_DCLK_100_MULT, FRQ, IVB_MAX_DCLK_100_MULT); |
| 33 | |
| 34 | if (ctrl->base_freq == 133) |
| 35 | return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT); |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 36 | |
| 37 | } else if (IS_SANDY_CPU(ctrl->cpu)) { |
| 38 | if (ctrl->base_freq == 133) |
| 39 | return clamp_u32(SNB_MIN_DCLK_133_MULT, FRQ, SNB_MAX_DCLK_133_MULT); |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 40 | } |
| 41 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 42 | die("Unsupported CPU or base frequency."); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 43 | } |
| 44 | |
Angel Pons | 2f3cc00 | 2020-11-11 18:49:31 +0100 | [diff] [blame] | 45 | /* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ |
| 46 | static u8 get_CWL(u32 tCK) |
| 47 | { |
| 48 | /* Get CWL based on tCK using the following rule */ |
| 49 | switch (tCK) { |
| 50 | case TCK_1333MHZ: |
| 51 | return 12; |
| 52 | |
| 53 | case TCK_1200MHZ: |
| 54 | case TCK_1100MHZ: |
| 55 | return 11; |
| 56 | |
| 57 | case TCK_1066MHZ: |
| 58 | case TCK_1000MHZ: |
| 59 | return 10; |
| 60 | |
| 61 | case TCK_933MHZ: |
| 62 | case TCK_900MHZ: |
| 63 | return 9; |
| 64 | |
| 65 | case TCK_800MHZ: |
| 66 | case TCK_700MHZ: |
| 67 | return 8; |
| 68 | |
| 69 | case TCK_666MHZ: |
| 70 | return 7; |
| 71 | |
| 72 | case TCK_533MHZ: |
| 73 | return 6; |
| 74 | |
| 75 | default: |
| 76 | return 5; |
| 77 | } |
| 78 | } |
| 79 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 80 | /* Get REFI based on frequency index, tREFI = 7.8usec */ |
| 81 | static u32 get_REFI(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 82 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 83 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 84 | return frq_refi_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 85 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 86 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 87 | return frq_refi_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 88 | } |
| 89 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 90 | /* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */ |
| 91 | static u8 get_XSOffset(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 92 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 93 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 94 | return frq_xs_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 95 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 96 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 97 | return frq_xs_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 98 | } |
| 99 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 100 | /* Get MOD based on frequency index */ |
| 101 | static u8 get_MOD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 102 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 103 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 104 | return frq_mod_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 105 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 106 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 107 | return frq_mod_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 108 | } |
| 109 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 110 | /* Get Write Leveling Output delay based on frequency index */ |
| 111 | static u8 get_WLO(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 112 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 113 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 114 | return frq_wlo_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 115 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 116 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 117 | return frq_wlo_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 118 | } |
| 119 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 120 | /* Get CKE based on frequency index */ |
| 121 | static u8 get_CKE(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 122 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 123 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 124 | return frq_cke_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 125 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 126 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 127 | return frq_cke_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 128 | } |
| 129 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 130 | /* Get XPDLL based on frequency index */ |
| 131 | static u8 get_XPDLL(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 132 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 133 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 134 | return frq_xpdll_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 135 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 136 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 137 | return frq_xpdll_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 138 | } |
| 139 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 140 | /* Get XP based on frequency index */ |
| 141 | static u8 get_XP(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 142 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 143 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 144 | return frq_xp_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 145 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 146 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 147 | return frq_xp_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 148 | } |
| 149 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 150 | /* Get AONPD based on frequency index */ |
| 151 | static u8 get_AONPD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 152 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 153 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 154 | return frq_aonpd_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 155 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 156 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 157 | return frq_aonpd_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 158 | } |
| 159 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 160 | /* Get COMP2 based on frequency index */ |
| 161 | static u32 get_COMP2(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 162 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 163 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 164 | return frq_comp2_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 165 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 166 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 167 | return frq_comp2_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 168 | } |
| 169 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 170 | static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 171 | { |
| 172 | if (ctrl->tCK <= TCK_1200MHZ) { |
| 173 | ctrl->tCK = TCK_1200MHZ; |
| 174 | ctrl->base_freq = 100; |
| 175 | } else if (ctrl->tCK <= TCK_1100MHZ) { |
| 176 | ctrl->tCK = TCK_1100MHZ; |
| 177 | ctrl->base_freq = 100; |
| 178 | } else if (ctrl->tCK <= TCK_1066MHZ) { |
| 179 | ctrl->tCK = TCK_1066MHZ; |
| 180 | ctrl->base_freq = 133; |
| 181 | } else if (ctrl->tCK <= TCK_1000MHZ) { |
| 182 | ctrl->tCK = TCK_1000MHZ; |
| 183 | ctrl->base_freq = 100; |
| 184 | } else if (ctrl->tCK <= TCK_933MHZ) { |
| 185 | ctrl->tCK = TCK_933MHZ; |
| 186 | ctrl->base_freq = 133; |
| 187 | } else if (ctrl->tCK <= TCK_900MHZ) { |
| 188 | ctrl->tCK = TCK_900MHZ; |
| 189 | ctrl->base_freq = 100; |
| 190 | } else if (ctrl->tCK <= TCK_800MHZ) { |
| 191 | ctrl->tCK = TCK_800MHZ; |
| 192 | ctrl->base_freq = 133; |
| 193 | } else if (ctrl->tCK <= TCK_700MHZ) { |
| 194 | ctrl->tCK = TCK_700MHZ; |
| 195 | ctrl->base_freq = 100; |
| 196 | } else if (ctrl->tCK <= TCK_666MHZ) { |
| 197 | ctrl->tCK = TCK_666MHZ; |
| 198 | ctrl->base_freq = 133; |
| 199 | } else if (ctrl->tCK <= TCK_533MHZ) { |
| 200 | ctrl->tCK = TCK_533MHZ; |
| 201 | ctrl->base_freq = 133; |
| 202 | } else if (ctrl->tCK <= TCK_400MHZ) { |
| 203 | ctrl->tCK = TCK_400MHZ; |
| 204 | ctrl->base_freq = 133; |
| 205 | } else { |
| 206 | ctrl->tCK = 0; |
| 207 | return; |
| 208 | } |
| 209 | |
| 210 | if (!ref_100mhz_support && ctrl->base_freq == 100) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 211 | /* Skip unsupported frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 212 | ctrl->tCK++; |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 213 | normalize_tclk(ctrl, ref_100mhz_support); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 214 | } |
| 215 | } |
| 216 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 217 | #define DEFAULT_TCK TCK_800MHZ |
| 218 | |
| 219 | static unsigned int get_mem_min_tck(void) |
| 220 | { |
| 221 | u32 reg32; |
| 222 | u8 rev; |
| 223 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 224 | |
| 225 | /* Actually, config of MCH or Host Bridge */ |
| 226 | cfg = config_of_soc(); |
| 227 | |
| 228 | /* If non-zero, it was set in the devicetree */ |
| 229 | if (cfg->max_mem_clock_mhz) { |
| 230 | |
| 231 | if (cfg->max_mem_clock_mhz >= 1066) |
| 232 | return TCK_1066MHZ; |
| 233 | |
| 234 | else if (cfg->max_mem_clock_mhz >= 933) |
| 235 | return TCK_933MHZ; |
| 236 | |
| 237 | else if (cfg->max_mem_clock_mhz >= 800) |
| 238 | return TCK_800MHZ; |
| 239 | |
| 240 | else if (cfg->max_mem_clock_mhz >= 666) |
| 241 | return TCK_666MHZ; |
| 242 | |
| 243 | else if (cfg->max_mem_clock_mhz >= 533) |
| 244 | return TCK_533MHZ; |
| 245 | |
| 246 | else |
| 247 | return TCK_400MHZ; |
| 248 | } |
| 249 | |
| 250 | if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) |
| 251 | return TCK_1333MHZ; |
| 252 | |
| 253 | rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); |
| 254 | |
| 255 | if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { |
| 256 | /* Read Capabilities A Register DMFC bits */ |
| 257 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 258 | reg32 &= 0x7; |
| 259 | |
| 260 | switch (reg32) { |
| 261 | case 7: return TCK_533MHZ; |
| 262 | case 6: return TCK_666MHZ; |
| 263 | case 5: return TCK_800MHZ; |
| 264 | /* Reserved */ |
| 265 | default: |
| 266 | break; |
| 267 | } |
| 268 | } else { |
| 269 | /* Read Capabilities B Register DMFC bits */ |
| 270 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
| 271 | reg32 = (reg32 >> 4) & 0x7; |
| 272 | |
| 273 | switch (reg32) { |
| 274 | case 7: return TCK_533MHZ; |
| 275 | case 6: return TCK_666MHZ; |
| 276 | case 5: return TCK_800MHZ; |
| 277 | case 4: return TCK_933MHZ; |
| 278 | case 3: return TCK_1066MHZ; |
| 279 | case 2: return TCK_1200MHZ; |
| 280 | case 1: return TCK_1333MHZ; |
| 281 | /* Reserved */ |
| 282 | default: |
| 283 | break; |
| 284 | } |
| 285 | } |
| 286 | return DEFAULT_TCK; |
| 287 | } |
| 288 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 289 | static void find_cas_tck(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 290 | { |
| 291 | u8 val; |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 292 | u32 reg32; |
| 293 | u8 ref_100mhz_support; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 294 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 295 | /* 100 MHz reference clock supported */ |
| 296 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame] | 297 | ref_100mhz_support = (reg32 >> 21) & 0x7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 298 | printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" |
| 299 | : "no"); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 300 | |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame] | 301 | printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); |
| 302 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 303 | ctrl->tCK = get_mem_min_tck(); |
| 304 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 305 | /* Find CAS latency */ |
| 306 | while (1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 307 | /* |
| 308 | * Normalising tCK before computing clock could potentially |
| 309 | * result in a lower selected CAS, which is desired. |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 310 | */ |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 311 | normalize_tclk(ctrl, ref_100mhz_support); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 312 | if (!(ctrl->tCK)) |
| 313 | die("Couldn't find compatible clock / CAS settings\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 314 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 315 | val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); |
| 316 | printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); |
| 317 | for (; val <= MAX_CAS; val++) |
| 318 | if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) |
| 319 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 320 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 321 | if (val == (MAX_CAS + 1)) { |
| 322 | ctrl->tCK++; |
| 323 | continue; |
| 324 | } else { |
| 325 | printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n"); |
| 326 | break; |
| 327 | } |
| 328 | } |
| 329 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 330 | /* Frequency multiplier */ |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 331 | ctrl->FRQ = get_FRQ(ctrl); |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 332 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 333 | printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 334 | printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); |
| 335 | ctrl->CAS = val; |
| 336 | } |
| 337 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 338 | static void dram_timing(ramctr_timing *ctrl) |
| 339 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 340 | /* |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 341 | * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133). |
| 342 | * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency. |
| 343 | */ |
| 344 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 345 | * On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800). |
| 346 | * Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency. |
| 347 | */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 348 | if (ctrl->tCK == TCK_1200MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 349 | ctrl->edge_offset[0] = 18; //XXX: guessed |
| 350 | ctrl->edge_offset[1] = 8; |
| 351 | ctrl->edge_offset[2] = 8; |
| 352 | ctrl->timC_offset[0] = 20; //XXX: guessed |
| 353 | ctrl->timC_offset[1] = 8; |
| 354 | ctrl->timC_offset[2] = 8; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 355 | ctrl->pi_coding_threshold = 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 356 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 357 | } else if (ctrl->tCK == TCK_1100MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 358 | ctrl->edge_offset[0] = 17; //XXX: guessed |
| 359 | ctrl->edge_offset[1] = 7; |
| 360 | ctrl->edge_offset[2] = 7; |
| 361 | ctrl->timC_offset[0] = 19; //XXX: guessed |
| 362 | ctrl->timC_offset[1] = 7; |
| 363 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 364 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 365 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 366 | } else if (ctrl->tCK == TCK_1066MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 367 | ctrl->edge_offset[0] = 16; |
| 368 | ctrl->edge_offset[1] = 7; |
| 369 | ctrl->edge_offset[2] = 7; |
| 370 | ctrl->timC_offset[0] = 18; |
| 371 | ctrl->timC_offset[1] = 7; |
| 372 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 373 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 374 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 375 | } else if (ctrl->tCK == TCK_1000MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 376 | ctrl->edge_offset[0] = 15; //XXX: guessed |
| 377 | ctrl->edge_offset[1] = 6; |
| 378 | ctrl->edge_offset[2] = 6; |
| 379 | ctrl->timC_offset[0] = 17; //XXX: guessed |
| 380 | ctrl->timC_offset[1] = 6; |
| 381 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 382 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 383 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 384 | } else if (ctrl->tCK == TCK_933MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 385 | ctrl->edge_offset[0] = 14; |
| 386 | ctrl->edge_offset[1] = 6; |
| 387 | ctrl->edge_offset[2] = 6; |
| 388 | ctrl->timC_offset[0] = 15; |
| 389 | ctrl->timC_offset[1] = 6; |
| 390 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 391 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 392 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 393 | } else if (ctrl->tCK == TCK_900MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 394 | ctrl->edge_offset[0] = 14; //XXX: guessed |
| 395 | ctrl->edge_offset[1] = 6; |
| 396 | ctrl->edge_offset[2] = 6; |
| 397 | ctrl->timC_offset[0] = 15; //XXX: guessed |
| 398 | ctrl->timC_offset[1] = 6; |
| 399 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 400 | ctrl->pi_coding_threshold = 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 401 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 402 | } else if (ctrl->tCK == TCK_800MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 403 | ctrl->edge_offset[0] = 13; |
| 404 | ctrl->edge_offset[1] = 5; |
| 405 | ctrl->edge_offset[2] = 5; |
| 406 | ctrl->timC_offset[0] = 14; |
| 407 | ctrl->timC_offset[1] = 5; |
| 408 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 409 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 410 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 411 | } else if (ctrl->tCK == TCK_700MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 412 | ctrl->edge_offset[0] = 13; //XXX: guessed |
| 413 | ctrl->edge_offset[1] = 5; |
| 414 | ctrl->edge_offset[2] = 5; |
| 415 | ctrl->timC_offset[0] = 14; //XXX: guessed |
| 416 | ctrl->timC_offset[1] = 5; |
| 417 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 418 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 419 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 420 | } else if (ctrl->tCK == TCK_666MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 421 | ctrl->edge_offset[0] = 10; |
| 422 | ctrl->edge_offset[1] = 4; |
| 423 | ctrl->edge_offset[2] = 4; |
| 424 | ctrl->timC_offset[0] = 11; |
| 425 | ctrl->timC_offset[1] = 4; |
| 426 | ctrl->timC_offset[2] = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 427 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 428 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 429 | } else if (ctrl->tCK == TCK_533MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 430 | ctrl->edge_offset[0] = 8; |
| 431 | ctrl->edge_offset[1] = 3; |
| 432 | ctrl->edge_offset[2] = 3; |
| 433 | ctrl->timC_offset[0] = 9; |
| 434 | ctrl->timC_offset[1] = 3; |
| 435 | ctrl->timC_offset[2] = 3; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 436 | ctrl->pi_coding_threshold = 17; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 437 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 438 | } else { /* TCK_400MHZ */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 439 | ctrl->edge_offset[0] = 6; |
| 440 | ctrl->edge_offset[1] = 2; |
| 441 | ctrl->edge_offset[2] = 2; |
| 442 | ctrl->timC_offset[0] = 6; |
| 443 | ctrl->timC_offset[1] = 2; |
| 444 | ctrl->timC_offset[2] = 2; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 445 | ctrl->pi_coding_threshold = 17; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | /* Initial phase between CLK/CMD pins */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 449 | ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 450 | |
| 451 | /* DLL_CONFIG_MDLL_W_TIMER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 452 | ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 453 | |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 454 | if (ctrl->tCWL) |
| 455 | ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); |
| 456 | else |
| 457 | ctrl->CWL = get_CWL(ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 458 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 459 | printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); |
| 460 | |
| 461 | /* Find tRCD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 462 | ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 463 | printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); |
| 464 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 465 | ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 466 | printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); |
| 467 | |
| 468 | /* Find tRAS */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 469 | ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 470 | printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); |
| 471 | |
| 472 | /* Find tWR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 473 | ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 474 | printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); |
| 475 | |
| 476 | /* Find tFAW */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 477 | ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 478 | printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); |
| 479 | |
| 480 | /* Find tRRD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 481 | ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 482 | printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); |
| 483 | |
| 484 | /* Find tRTP */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 485 | ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 486 | printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); |
| 487 | |
| 488 | /* Find tWTR */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 489 | ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 490 | printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); |
| 491 | |
| 492 | /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 493 | ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 494 | printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); |
| 495 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 496 | ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); |
| 497 | ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); |
| 498 | ctrl->tXSOffset = get_XSOffset(ctrl->FRQ, ctrl->base_freq); |
| 499 | ctrl->tWLO = get_WLO(ctrl->FRQ, ctrl->base_freq); |
| 500 | ctrl->tCKE = get_CKE(ctrl->FRQ, ctrl->base_freq); |
| 501 | ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); |
| 502 | ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); |
| 503 | ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 504 | } |
| 505 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 506 | static void dram_freq(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 507 | { |
| 508 | if (ctrl->tCK > TCK_400MHZ) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 509 | printk(BIOS_ERR, |
| 510 | "DRAM frequency is under lowest supported frequency (400 MHz). " |
| 511 | "Increasing to 400 MHz as last resort"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 512 | ctrl->tCK = TCK_400MHZ; |
| 513 | } |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 514 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 515 | while (1) { |
| 516 | u8 val2; |
| 517 | u32 reg1 = 0; |
| 518 | |
| 519 | /* Step 1 - Set target PCU frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 520 | find_cas_tck(ctrl); |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 521 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 522 | /* |
| 523 | * The PLL will never lock if the required frequency is already set. |
| 524 | * Exit early to prevent a system hang. |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 525 | */ |
| 526 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 527 | val2 = (u8) reg1; |
| 528 | if (val2) |
| 529 | return; |
| 530 | |
| 531 | /* Step 2 - Select frequency in the MCU */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 532 | reg1 = ctrl->FRQ; |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 533 | if (ctrl->base_freq == 100) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 534 | reg1 |= 0x100; /* Enable 100Mhz REF clock */ |
| 535 | |
| 536 | reg1 |= 0x80000000; /* set running bit */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 537 | MCHBAR32(MC_BIOS_REQ) = reg1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 538 | int i = 0; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 539 | printk(BIOS_DEBUG, "PLL busy... "); |
| 540 | while (reg1 & 0x80000000) { |
| 541 | udelay(10); |
| 542 | i++; |
| 543 | reg1 = MCHBAR32(MC_BIOS_REQ); |
| 544 | } |
| 545 | printk(BIOS_DEBUG, "done in %d us\n", i * 10); |
| 546 | |
| 547 | /* Step 3 - Verify lock frequency */ |
| 548 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 549 | val2 = (u8) reg1; |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 550 | if (val2 >= ctrl->FRQ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 551 | printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", |
| 552 | (1000 << 8) / ctrl->tCK); |
| 553 | return; |
| 554 | } |
| 555 | printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); |
| 556 | ctrl->tCK++; |
| 557 | } |
| 558 | } |
| 559 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 560 | static void dram_ioregs(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 561 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 562 | u32 reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 563 | |
| 564 | int channel; |
| 565 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 566 | /* IO clock */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 567 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 568 | MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 569 | } |
| 570 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 571 | /* IO command */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 572 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 573 | MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 574 | } |
| 575 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 576 | /* IO control */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 577 | FOR_ALL_POPULATED_CHANNELS { |
| 578 | program_timings(ctrl, channel); |
| 579 | } |
| 580 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 581 | /* Perform RCOMP */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 582 | printram("RCOMP..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 583 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 584 | ; |
| 585 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 586 | printram("done\n"); |
| 587 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 588 | /* Set COMP2 */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 589 | MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->FRQ, ctrl->base_freq); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 590 | printram("COMP2 done\n"); |
| 591 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 592 | /* Set COMP1 */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 593 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 594 | reg = MCHBAR32(CRCOMPOFST1_ch(channel)); |
| 595 | reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ |
| 596 | reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ |
| 597 | reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 598 | MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 599 | } |
| 600 | printram("COMP1 done\n"); |
| 601 | |
| 602 | printram("FORCE RCOMP and wait 20us..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 603 | MCHBAR32(M_COMP) |= (1 << 8); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 604 | udelay(20); |
| 605 | printram("done\n"); |
| 606 | } |
| 607 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 608 | int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 609 | { |
| 610 | int err; |
| 611 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 612 | printk(BIOS_DEBUG, "Starting %s Bridge RAM training (%s).\n", |
| 613 | IS_SANDY_CPU(ctrl->cpu) ? "Sandy" : "Ivy", |
| 614 | fast_boot ? "fast boot" : "full initialization"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 615 | |
| 616 | if (!fast_boot) { |
| 617 | /* Find fastest common supported parameters */ |
| 618 | dram_find_common_params(ctrl); |
| 619 | |
| 620 | dram_dimm_mapping(ctrl); |
| 621 | } |
| 622 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 623 | /* Set MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 624 | dram_freq(ctrl); |
| 625 | |
| 626 | if (!fast_boot) { |
| 627 | /* Calculate timings */ |
| 628 | dram_timing(ctrl); |
| 629 | } |
| 630 | |
| 631 | /* Set version register */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 632 | MCHBAR32(MRC_REVISION) = 0xc04eb002; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 633 | |
| 634 | /* Enable crossover */ |
| 635 | dram_xover(ctrl); |
| 636 | |
| 637 | /* Set timing and refresh registers */ |
| 638 | dram_timing_regs(ctrl); |
| 639 | |
| 640 | /* Power mode preset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 641 | MCHBAR32(PM_THML_STAT) = 0x5500; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 642 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 643 | /* Set scheduler chicken bits */ |
| 644 | MCHBAR32(SCHED_CBIT) = 0x10100005; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 645 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 646 | /* Set up watermarks and starvation counter */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 647 | set_wmm_behavior(ctrl->cpu); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 648 | |
| 649 | /* Clear IO reset bit */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 650 | MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 651 | |
| 652 | /* Set MAD-DIMM registers */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 653 | dram_dimm_set_mapping(ctrl, 1); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 654 | printk(BIOS_DEBUG, "Done dimm mapping\n"); |
| 655 | |
| 656 | /* Zone config */ |
| 657 | dram_zones(ctrl, 1); |
| 658 | |
| 659 | /* Set memory map */ |
| 660 | dram_memorymap(ctrl, me_uma_size); |
| 661 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 662 | |
| 663 | /* Set IO registers */ |
| 664 | dram_ioregs(ctrl); |
| 665 | printk(BIOS_DEBUG, "Done io registers\n"); |
| 666 | |
| 667 | udelay(1); |
| 668 | |
| 669 | if (fast_boot) { |
| 670 | restore_timings(ctrl); |
| 671 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 672 | /* Do JEDEC DDR3 reset sequence */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 673 | dram_jedecreset(ctrl); |
| 674 | printk(BIOS_DEBUG, "Done jedec reset\n"); |
| 675 | |
| 676 | /* MRS commands */ |
| 677 | dram_mrscommands(ctrl); |
| 678 | printk(BIOS_DEBUG, "Done MRS commands\n"); |
| 679 | |
| 680 | /* Prepare for memory training */ |
| 681 | prepare_training(ctrl); |
| 682 | |
Angel Pons | 7f5a97c | 2020-11-13 16:58:46 +0100 | [diff] [blame] | 683 | err = receive_enable_calibration(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 684 | if (err) |
| 685 | return err; |
| 686 | |
Angel Pons | 068c259 | 2020-11-14 01:31:15 +0100 | [diff] [blame] | 687 | err = read_mpr_training(ctrl); |
| 688 | if (err) |
| 689 | return err; |
| 690 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 691 | err = write_training(ctrl); |
| 692 | if (err) |
| 693 | return err; |
| 694 | |
| 695 | printram("CP5a\n"); |
| 696 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 697 | printram("CP5b\n"); |
| 698 | |
| 699 | err = command_training(ctrl); |
| 700 | if (err) |
| 701 | return err; |
| 702 | |
| 703 | printram("CP5c\n"); |
| 704 | |
| 705 | err = discover_edges_write(ctrl); |
| 706 | if (err) |
| 707 | return err; |
| 708 | |
| 709 | err = discover_timC_write(ctrl); |
| 710 | if (err) |
| 711 | return err; |
| 712 | |
| 713 | normalize_training(ctrl); |
| 714 | } |
| 715 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 716 | set_read_write_timings(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 717 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 718 | if (!s3resume) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 719 | err = channel_test(ctrl); |
| 720 | if (err) |
| 721 | return err; |
| 722 | } |
| 723 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 724 | /* Set MAD-DIMM registers */ |
| 725 | dram_dimm_set_mapping(ctrl, 0); |
| 726 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 727 | return 0; |
| 728 | } |