Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 1 | config SOC_INTEL_METEORLAKE |
| 2 | bool |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 3 | help |
| 4 | Intel Meteorlake support |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 5 | |
| 6 | if SOC_INTEL_METEORLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 11 | select ARCH_X86 |
| 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 13 | select CACHE_MRC_SETTINGS |
| 14 | select CPU_INTEL_COMMON |
Subrata Banik | 1f5154e | 2022-12-06 18:21:50 +0530 | [diff] [blame] | 15 | select CPU_INTEL_COMMON_VOLTAGE |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 16 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 17 | select CPU_SUPPORTS_INTEL_TME |
| 18 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Subrata Banik | e96993d | 2022-07-09 22:06:45 +0000 | [diff] [blame] | 19 | select DEFAULT_X2APIC_LATE_WORKAROUND |
Saurabh Mishra | 16ba8e1 | 2022-11-22 13:35:08 +0530 | [diff] [blame] | 20 | select DISPLAY_FSP_VERSION_INFO_2 |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 21 | select DRIVERS_USB_ACPI |
Sean Rhodes | 7bbc9a5 | 2022-07-18 11:31:00 +0100 | [diff] [blame] | 22 | select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 23 | select FSP_COMPRESS_FSP_S_LZ4 |
| 24 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 25 | select FSP_M_XIP |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 26 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 27 | select FSP_USES_CB_DEBUG_EVENT_HANDLER |
| 28 | select FSPS_HAS_ARCH_UPD |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 29 | select GENERIC_GPIO_LIB |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 30 | select HAVE_DEBUG_RAM_SETUP |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 31 | select HAVE_FSP_GOP |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 32 | select HAVE_INTEL_COMPLIANCE_TEST_MODE |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 33 | select HAVE_SMI_HANDLER |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 34 | select IDT_IN_EVERY_STAGE |
Subrata Banik | 0d6d228 | 2022-07-09 22:17:02 +0000 | [diff] [blame] | 35 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 36 | select INTEL_GMA_ACPI |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 37 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Dinesh Gehlot | 0d76a30 | 2022-12-09 07:24:08 +0000 | [diff] [blame] | 38 | select INTEL_GMA_OPREGION_2_1 |
Subrata Banik | 0d6d228 | 2022-07-09 22:17:02 +0000 | [diff] [blame] | 39 | select IOAPIC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 40 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | 0d6d228 | 2022-07-09 22:17:02 +0000 | [diff] [blame] | 41 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 0d6d228 | 2022-07-09 22:17:02 +0000 | [diff] [blame] | 42 | select PARALLEL_MP_AP_WORK |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 43 | select PLATFORM_USES_FSP2_3 |
| 44 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 45 | select SOC_INTEL_COMMON |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_ACPI |
| 49 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Sridhar Siricilla | d1237da | 2022-12-09 01:13:45 +0530 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Subrata Banik | 2a2488f | 2022-12-05 20:28:42 +0530 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 54 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_CAR |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Subrata Banik | 00b682e | 2022-09-14 17:58:51 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_CPU |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 60 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
| 61 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 62 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | bae1de1 | 2022-07-21 13:43:37 +0000 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR |
Jamie Ryu | b6c32d7 | 2022-08-03 01:13:33 -0700 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | 98b6967 | 2022-11-23 14:46:16 +0530 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_IPU |
| 69 | select SOC_INTEL_COMMON_BLOCK_IOE_P2SB |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
| 73 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
| 74 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_BLOCK_SA |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 76 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 77 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 78 | select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 79 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 80 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
| 81 | select SOC_INTEL_COMMON_BASECODE |
| 82 | select SOC_INTEL_COMMON_FSP_RESET |
Angel Pons | eb90c51 | 2022-07-18 14:41:24 +0200 | [diff] [blame] | 83 | select SOC_INTEL_COMMON_PCH_CLIENT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 84 | select SOC_INTEL_COMMON_RESET |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_BLOCK_IOC |
Subrata Banik | b955304 | 2022-11-24 23:48:13 +0530 | [diff] [blame] | 86 | select SOC_INTEL_CSE_SEND_EOP_LATE |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 87 | select SOC_INTEL_CSE_SET_EOP |
Wonkyu Kim | a888489 | 2022-08-10 14:10:03 -0700 | [diff] [blame] | 88 | select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 89 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 90 | select SSE2 |
| 91 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 92 | select TSC_MONOTONIC_TIMER |
| 93 | select UDELAY_TSC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 94 | select UDK_202111_BINDING |
Subrata Banik | 6a22c5f | 2022-11-21 17:39:57 +0530 | [diff] [blame] | 95 | select X86_INIT_NEED_1_SIPI |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 96 | |
Subrata Banik | 8e15859 | 2022-12-13 12:16:52 +0530 | [diff] [blame] | 97 | config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT |
| 98 | bool |
| 99 | default y |
| 100 | select SOC_INTEL_COMMON_BLOCK_TCSS |
| 101 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 102 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 103 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
| 104 | |
Subrata Banik | 4300421 | 2022-12-13 12:20:47 +0530 | [diff] [blame] | 105 | config METEORLAKE_CAR_ENHANCED_NEM |
| 106 | bool |
| 107 | default y if !INTEL_CAR_NEM |
| 108 | select INTEL_CAR_NEM_ENHANCED |
| 109 | select CAR_HAS_SF_MASKS |
| 110 | select COS_MAPPED_TO_MSB |
| 111 | select CAR_HAS_L3_PROTECTED_WAYS |
| 112 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 113 | config MAX_CPUS |
| 114 | int |
| 115 | default 22 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 116 | |
| 117 | config DCACHE_RAM_BASE |
| 118 | default 0xfef00000 |
| 119 | |
| 120 | config DCACHE_RAM_SIZE |
| 121 | default 0xc0000 |
| 122 | help |
| 123 | The size of the cache-as-ram region required during bootblock |
| 124 | and/or romstage. |
| 125 | |
| 126 | config DCACHE_BSP_STACK_SIZE |
| 127 | hex |
| 128 | default 0x80400 |
| 129 | help |
| 130 | The amount of anticipated stack usage in CAR by bootblock and |
| 131 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 132 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
| 133 | (~1KiB). |
| 134 | |
| 135 | config FSP_TEMP_RAM_SIZE |
| 136 | hex |
| 137 | default 0x20000 |
| 138 | help |
| 139 | The amount of anticipated heap usage in CAR by FSP. |
| 140 | Refer to Platform FSP integration guide document to know |
| 141 | the exact FSP requirement for Heap setup. |
| 142 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 143 | config CHIPSET_DEVICETREE |
| 144 | string |
| 145 | default "soc/intel/meteorlake/chipset.cb" |
| 146 | |
| 147 | config EXT_BIOS_WIN_BASE |
| 148 | default 0xf8000000 |
| 149 | |
| 150 | config EXT_BIOS_WIN_SIZE |
| 151 | default 0x2000000 |
| 152 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 153 | config IFD_CHIPSET |
| 154 | string |
Subrata Banik | d624e74 | 2022-07-06 06:45:57 +0000 | [diff] [blame] | 155 | default "mtl" |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 156 | |
| 157 | config IED_REGION_SIZE |
| 158 | hex |
| 159 | default 0x400000 |
| 160 | |
| 161 | config HEAP_SIZE |
| 162 | hex |
| 163 | default 0x10000 |
| 164 | |
Subrata Banik | a33bcb9 | 2022-07-06 07:07:26 +0000 | [diff] [blame] | 165 | # Intel recommends reserving the PCIe TBT root port resources as below: |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 166 | # - 42 buses |
| 167 | # - 194 MiB Non-prefetchable memory |
| 168 | # - 448 MiB Prefetchable memory |
| 169 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| 170 | |
| 171 | config PCIEXP_HOTPLUG_BUSES |
| 172 | int |
| 173 | default 42 |
| 174 | |
| 175 | config PCIEXP_HOTPLUG_MEM |
| 176 | hex |
| 177 | default 0xc200000 |
| 178 | |
| 179 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 180 | hex |
| 181 | default 0x1c000000 |
| 182 | |
| 183 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| 184 | |
| 185 | config MAX_TBT_ROOT_PORTS |
| 186 | int |
| 187 | default 4 |
| 188 | |
| 189 | config MAX_ROOT_PORTS |
| 190 | int |
| 191 | default 12 |
| 192 | |
| 193 | config MAX_PCIE_CLOCK_SRC |
| 194 | int |
| 195 | default 9 |
| 196 | |
| 197 | config SMM_TSEG_SIZE |
| 198 | hex |
| 199 | default 0x800000 |
| 200 | |
| 201 | config SMM_RESERVED_SIZE |
| 202 | hex |
| 203 | default 0x200000 |
| 204 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 205 | config PCR_BASE_ADDRESS |
| 206 | hex |
| 207 | default 0xe0000000 |
| 208 | help |
| 209 | This option allows you to select MMIO Base Address of sideband bus. |
| 210 | |
| 211 | config ECAM_MMCONF_BASE_ADDRESS |
| 212 | default 0xc0000000 |
| 213 | |
Sridhar Siricilla | d9c8269 | 2023-01-05 17:08:17 +0530 | [diff] [blame] | 214 | config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR |
| 215 | int |
| 216 | default 125 |
| 217 | |
| 218 | config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR |
| 219 | int |
| 220 | default 100 |
| 221 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 222 | config CPU_BCLK_MHZ |
| 223 | int |
| 224 | default 100 |
| 225 | |
| 226 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 227 | int |
| 228 | default 120 |
| 229 | |
| 230 | config CPU_XTAL_HZ |
| 231 | default 38400000 |
| 232 | |
| 233 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 234 | int |
| 235 | default 133 |
| 236 | |
| 237 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 238 | int |
Subrata Banik | e54a8fd | 2022-07-06 12:54:48 +0000 | [diff] [blame] | 239 | default 3 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 240 | |
| 241 | config SOC_INTEL_I2C_DEV_MAX |
| 242 | int |
| 243 | default 6 |
| 244 | |
| 245 | config SOC_INTEL_UART_DEV_MAX |
| 246 | int |
| 247 | default 3 |
| 248 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 249 | config SOC_INTEL_USB2_DEV_MAX |
| 250 | int |
| 251 | default 10 |
| 252 | |
| 253 | config SOC_INTEL_USB3_DEV_MAX |
| 254 | int |
| 255 | default 2 |
| 256 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 257 | config CONSOLE_UART_BASE_ADDRESS |
| 258 | hex |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 259 | default 0xfe02c000 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 260 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 261 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 262 | config VBT_DATA_SIZE_KB |
| 263 | int |
| 264 | default 9 |
| 265 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 266 | # Clock divider parameters for 115200 baud rate |
Angel Pons | 054ff5e | 2022-06-26 10:19:53 +0200 | [diff] [blame] | 267 | # Baudrate = (UART source clock * M) /(N *16) |
Wonkyu Kim | 60d9b89 | 2022-10-10 23:01:38 -0700 | [diff] [blame] | 268 | # MTL UART source clock: 100MHz |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 269 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 270 | hex |
| 271 | default 0x25a |
| 272 | |
| 273 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 274 | hex |
| 275 | default 0x7fff |
| 276 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 277 | config VBOOT |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 278 | select VBOOT_SEPARATE_VERSTAGE |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 279 | select VBOOT_MUST_REQUEST_DISPLAY |
| 280 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 281 | select VBOOT_VBNV_CMOS |
| 282 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 283 | select VBOOT_X86_SHA256_ACCELERATION |
| 284 | |
Subrata Banik | febd3d7 | 2022-05-30 13:59:25 +0530 | [diff] [blame] | 285 | # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| 286 | # hashing time as well as read time. |
| 287 | config VBOOT_HASH_BLOCK_SIZE |
| 288 | hex |
| 289 | default 0x1000 |
| 290 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 291 | config CBFS_SIZE |
| 292 | hex |
| 293 | default 0x200000 |
| 294 | |
| 295 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 296 | hex |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 297 | default 0x1400 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 298 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 299 | config FSP_HEADER_PATH |
| 300 | string "Location of FSP headers" |
| 301 | default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/" |
| 302 | |
| 303 | config FSP_FD_PATH |
| 304 | string |
| 305 | depends on FSP_USE_REPO |
| 306 | default "3rdparty/fsp/MeteorLakeFspBinPkg/Fsp.fd" |
| 307 | |
| 308 | config SOC_INTEL_METEORLAKE_DEBUG_CONSENT |
| 309 | int "Debug Consent for MTL" |
| 310 | # USB DBC is more common for developers so make this default to 3 if |
| 311 | # SOC_INTEL_DEBUG_CONSENT=y |
Subrata Banik | 653e157 | 2022-07-20 12:26:24 +0000 | [diff] [blame] | 312 | default 3 if SOC_INTEL_DEBUG_CONSENT |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 313 | default 0 |
| 314 | help |
| 315 | This is to control debug interface on SOC. |
| 316 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 317 | PlatformDebugConsent in FspmUpd.h has the details. |
| 318 | |
| 319 | Desired platform debug type are |
| 320 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 321 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 322 | 6:Enable (2-wire DCI OOB), 7:Manual |
| 323 | |
| 324 | config DATA_BUS_WIDTH |
| 325 | int |
| 326 | default 128 |
| 327 | |
| 328 | config DIMMS_PER_CHANNEL |
| 329 | int |
| 330 | default 2 |
| 331 | |
| 332 | config MRC_CHANNEL_WIDTH |
| 333 | int |
| 334 | default 16 |
| 335 | |
Martin Roth | f3a6729 | 2023-01-10 09:58:46 -0700 | [diff] [blame] | 336 | config CHROMEOS |
| 337 | select DEFAULT_SOFTWARE_CONNECTION_MANAGER |
Sean Rhodes | 060df17 | 2022-05-21 10:39:27 +0100 | [diff] [blame] | 338 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 339 | config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET |
| 340 | hex |
| 341 | default 0x800000 |
| 342 | |
Subrata Banik | 7c4789d | 2022-07-09 22:41:48 +0000 | [diff] [blame] | 343 | choice |
| 344 | prompt "Multiprocessor (MP) Initialization configuration to use" |
| 345 | default MTL_USE_FSP_MP_INIT |
| 346 | |
| 347 | config MTL_USE_FSP_MP_INIT |
| 348 | bool "Use FSP MP init" |
| 349 | select MP_SERVICES_PPI_V2 |
| 350 | help |
| 351 | Upon selection, coreboot brings APs from reset and the FSP runs feature programming. |
| 352 | |
| 353 | config MTL_USE_COREBOOT_MP_INIT |
| 354 | bool "Use coreboot MP init" |
Subrata Banik | 848c37d | 2022-12-09 13:38:26 +0530 | [diff] [blame] | 355 | # FSP assumes ownership of the APs (Application Processors) |
| 356 | # upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. |
| 357 | # Hence, select `MP_SERVICES_PPI_V2_NOOP` config to pass a valid |
| 358 | # pointer to the CpuMpPpi UPD with FSP_UNSUPPORTED type APIs. |
| 359 | # This will protect APs from getting hijacked by FSP while coreboot |
| 360 | # decides to set SkipMpInit UPD. |
| 361 | select MP_SERVICES_PPI_V2_NOOP |
Subrata Banik | 7c4789d | 2022-07-09 22:41:48 +0000 | [diff] [blame] | 362 | select RELOAD_MICROCODE_PATCH |
| 363 | help |
Sridhar Siricilla | 3741e99 | 2022-08-16 21:52:32 +0530 | [diff] [blame] | 364 | Upon selection, coreboot performs MP Initialization that includes feature programming. |
Subrata Banik | 7c4789d | 2022-07-09 22:41:48 +0000 | [diff] [blame] | 365 | |
| 366 | endchoice |
| 367 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 368 | endif |