Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 2 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
| 7 | #include <acpi/acpi_ivrs.h> |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Felix Held | 61dd31c | 2023-06-05 19:38:36 +0200 | [diff] [blame] | 9 | #include <arch/vga.h> |
Elyes HAOUAS | 146d0c2 | 2020-07-22 11:47:08 +0200 | [diff] [blame] | 10 | #include <types.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 11 | #include <device/device.h> |
| 12 | #include <device/pci.h> |
| 13 | #include <device/pci_ids.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 14 | #include <string.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 15 | #include <stdlib.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 16 | #include <lib.h> |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 17 | #include <cpu/x86/mp.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 18 | #include <Porting.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 19 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 20 | #include <cpu/amd/msr.h> |
| 21 | #include <cpu/amd/mtrr.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 22 | #include <acpi/acpigen.h> |
Angel Pons | ec5cf15 | 2020-11-10 20:42:07 +0100 | [diff] [blame] | 23 | #include <northbridge/amd/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 24 | #include <northbridge/amd/agesa/agesa_helper.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 25 | #include <southbridge/amd/pi/hudson/pci_devs.h> |
Arthur Heymans | 44807ac | 2022-09-13 12:43:37 +0200 | [diff] [blame] | 26 | #include <amdblocks/cpu.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 27 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 28 | #define PCIE_CAP_AER BIT(5) |
| 29 | #define PCIE_CAP_ACS BIT(6) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 30 | |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 31 | static int get_dram_base_limit(resource_t *basek, resource_t *limitk) |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 32 | { |
| 33 | u32 temp; |
| 34 | |
Felix Held | 7a83ab7 | 2023-12-16 23:10:50 +0100 | [diff] [blame^] | 35 | temp = pci_read_config32(DEV_PTR(ht_1), 0x40); //[39:24] at [31:16] |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 36 | if (!(temp & 1)) |
| 37 | return 0; // this memory range is not enabled |
| 38 | /* |
| 39 | * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits |
| 40 | * for physical address and the convert to KiB by shifting 10 bits left |
| 41 | */ |
| 42 | *basek = ((temp & 0xffff0000)) >> (10 - 8); |
| 43 | /* |
| 44 | * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but |
| 45 | * ORed with 0xffff to get real limit before shifting. |
| 46 | */ |
Felix Held | 7a83ab7 | 2023-12-16 23:10:50 +0100 | [diff] [blame^] | 47 | temp = pci_read_config32(DEV_PTR(ht_1), 0x44); //[39:24] at [31:16] |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 48 | *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); |
| 49 | *limitk += 1; // round up last byte |
| 50 | |
| 51 | return 1; |
| 52 | } |
| 53 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 54 | static void add_fixed_resources(struct device *dev, int index) |
| 55 | { |
| 56 | /* Reserve everything between A segment and 1MB: |
| 57 | * |
| 58 | * 0xa0000 - 0xbffff: legacy VGA |
| 59 | * 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) |
| 60 | */ |
Felix Held | 61dd31c | 2023-06-05 19:38:36 +0200 | [diff] [blame] | 61 | mmio_resource_kb(dev, index++, VGA_MMIO_BASE >> 10, VGA_MMIO_SIZE >> 10); |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 62 | reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 63 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 64 | /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ |
Felix Held | 7a83ab7 | 2023-12-16 23:10:50 +0100 | [diff] [blame^] | 65 | if (pci_read_config32(DEV_PTR(ht_2), 0x118) & (1 << 18)) { |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 66 | /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ |
| 67 | resource_t basek, limitk; |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 68 | if (!get_dram_base_limit(&basek, &limitk)) |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 69 | return; |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 70 | mmio_resource_kb(dev, index++, limitk, 16 * 1024); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 71 | } |
| 72 | } |
| 73 | |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 74 | static void nb_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 75 | { |
Kyösti Mälkki | 5d49038 | 2015-05-27 07:58:22 +0300 | [diff] [blame] | 76 | /* |
| 77 | * This MMCONF resource must be reserved in the PCI domain. |
| 78 | * It is not honored by the coreboot resource allocator if it is in |
| 79 | * the CPU_CLUSTER. |
| 80 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 81 | mmconf_resource(dev, MMIO_CONF_BASE); |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 82 | |
| 83 | /* NB IOAPIC2 resource */ |
Felix Held | 8f0075c | 2023-08-09 19:28:39 +0200 | [diff] [blame] | 84 | mmio_range(dev, IO_APIC2_ADDR, IO_APIC2_ADDR, 0x1000); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 85 | |
| 86 | add_fixed_resources(dev, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 87 | } |
| 88 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 89 | static void northbridge_init(struct device *dev) |
| 90 | { |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 91 | register_new_ioapic((u8 *)IO_APIC2_ADDR); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 92 | } |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 93 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 94 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 95 | { |
| 96 | void *addr, *current; |
| 97 | |
| 98 | /* Skip the HEST header. */ |
| 99 | current = (void *)(hest + 1); |
| 100 | |
| 101 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 102 | if (addr != NULL) |
| 103 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 104 | |
| 105 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 106 | if (addr != NULL) |
| 107 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 108 | |
| 109 | return (unsigned long)current; |
| 110 | } |
| 111 | |
Arthur Heymans | f9ee87f | 2023-06-07 15:29:02 +0200 | [diff] [blame] | 112 | static unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 113 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 114 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 115 | current = ALIGN_UP(current, 8); |
| 116 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 117 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 118 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 119 | ivhd_ioapic->reserved = 0x0000; |
| 120 | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 121 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 122 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 123 | ivhd_ioapic->handle = get_ioapic_id(VIO_APIC_VADDR); |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 124 | ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 125 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 126 | current += sizeof(ivrs_ivhd_special_t); |
| 127 | |
| 128 | ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 129 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 130 | ivhd_ioapic->reserved = 0x0000; |
| 131 | ivhd_ioapic->dte_setting = 0x00; |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 132 | ivhd_ioapic->handle = get_ioapic_id((u8 *)IO_APIC2_ADDR); |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 133 | ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); |
| 134 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 135 | current += sizeof(ivrs_ivhd_special_t); |
| 136 | |
| 137 | return current; |
| 138 | } |
| 139 | |
| 140 | static unsigned long ivhd_describe_hpet(unsigned long current) |
| 141 | { |
| 142 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 143 | current = ALIGN_UP(current, 8); |
| 144 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
| 145 | |
| 146 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 147 | ivhd_hpet->reserved = 0x0000; |
| 148 | ivhd_hpet->dte_setting = 0x00; |
| 149 | ivhd_hpet->handle = 0x00; |
| 150 | ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 151 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 152 | current += sizeof(ivrs_ivhd_special_t); |
| 153 | |
| 154 | return current; |
| 155 | } |
| 156 | |
| 157 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 158 | uint16_t end_devid, uint8_t setting) |
| 159 | { |
| 160 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 161 | current = ALIGN_UP(current, 4); |
| 162 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 163 | |
| 164 | /* Create the start range IVHD entry */ |
| 165 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 166 | ivhd_range->dev_id = start_devid; |
| 167 | ivhd_range->dte_setting = setting; |
| 168 | current += sizeof(ivrs_ivhd_generic_t); |
| 169 | |
| 170 | /* Create the end range IVHD entry */ |
| 171 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 172 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 173 | ivhd_range->dev_id = end_devid; |
| 174 | ivhd_range->dte_setting = setting; |
| 175 | current += sizeof(ivrs_ivhd_generic_t); |
| 176 | |
| 177 | return current; |
| 178 | } |
| 179 | |
| 180 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 181 | unsigned long *current, uint8_t type, uint8_t data) |
| 182 | { |
| 183 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 184 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 185 | *current = ALIGN_UP(*current, 4); |
| 186 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 187 | |
| 188 | ivhd_entry->type = type; |
| 189 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 190 | ivhd_entry->dte_setting = data; |
| 191 | *current += sizeof(ivrs_ivhd_generic_t); |
| 192 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 193 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 194 | *current = ALIGN_UP(*current, 8); |
| 195 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 196 | |
| 197 | ivhd_entry->type = type; |
| 198 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 199 | ivhd_entry->dte_setting = data; |
| 200 | ivhd_entry->reserved1 = 0; |
| 201 | ivhd_entry->reserved2 = 0; |
| 202 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 203 | (parent->bus->secondary << 8); |
| 204 | *current += sizeof(ivrs_ivhd_alias_t); |
| 205 | } |
| 206 | |
| 207 | return *current; |
| 208 | } |
| 209 | |
| 210 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
| 211 | unsigned long *current, uint16_t *ivhd_length) |
| 212 | { |
| 213 | unsigned int header_type, is_pcie; |
| 214 | unsigned long current_backup; |
| 215 | |
| 216 | header_type = dev->hdr_type & 0x7f; |
| 217 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 218 | |
| 219 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 220 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 221 | /* Device or Bridge is PCIe */ |
| 222 | current_backup = *current; |
| 223 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
| 224 | *ivhd_length += (*current - current_backup); |
| 225 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 226 | /* Device is legacy PCI or PCI-X */ |
| 227 | current_backup = *current; |
| 228 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
| 229 | *ivhd_length += (*current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 230 | } |
| 231 | } |
| 232 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 233 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 234 | unsigned int depth, int linknum, int8_t *root_level, |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 235 | unsigned long *current, uint16_t *ivhd_length) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 236 | { |
| 237 | struct device *sibling; |
| 238 | struct bus *link; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 239 | |
| 240 | if (!root_level) { |
| 241 | root_level = malloc(sizeof(int8_t)); |
| 242 | *root_level = -1; |
| 243 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 244 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 245 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 246 | |
| 247 | if ((dev->bus->secondary == 0x0) && |
| 248 | (dev->path.pci.devfn == 0x0)) |
| 249 | *root_level = depth; |
| 250 | |
| 251 | if ((*root_level != -1) && (dev->enabled)) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 252 | if (depth != *root_level) |
| 253 | ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 254 | } |
| 255 | } |
| 256 | |
| 257 | for (link = dev->link_list; link; link = link->next) |
| 258 | for (sibling = link->children; sibling; sibling = |
| 259 | sibling->sibling) |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 260 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
| 261 | current, ivhd_length); |
| 262 | |
| 263 | free(root_level); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 264 | } |
| 265 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 266 | #define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) |
| 267 | #define EFR_SUPPORT BIT(27) |
| 268 | |
| 269 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 270 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 271 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 272 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 273 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 274 | /* |
| 275 | * These devices should be already found by previous function. |
| 276 | * Do not perform NULL checks. |
| 277 | */ |
| 278 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 279 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 280 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 281 | /* |
| 282 | * In order to utilize all features, firmware should expose type 11h |
| 283 | * IVHD which supersedes the type 10h. |
| 284 | */ |
| 285 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 286 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 287 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 288 | /* Enable EFR */ |
| 289 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 290 | /* For type 11h bits 6 and 7 are reserved */ |
| 291 | ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; |
| 292 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 293 | /* BDF <bus>:00.2 */ |
| 294 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 295 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
| 296 | ivhd_11->capability_offset = 0x40; |
| 297 | ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 298 | ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
| 299 | ivhd_11->pci_segment_group = 0x0000; |
| 300 | ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 301 | ivhd_11->iommu_attributes.perf_counters = |
| 302 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; |
| 303 | ivhd_11->iommu_attributes.perf_counter_banks = |
| 304 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; |
| 305 | ivhd_11->iommu_attributes.msi_num_ppr = |
| 306 | (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 307 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 308 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { |
| 309 | ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); |
| 310 | ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); |
| 311 | } |
| 312 | |
| 313 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 314 | |
| 315 | /* Now repeat all the device entries from type 10h */ |
| 316 | current_backup = current; |
| 317 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 318 | ivhd_11->length += (current - current_backup); |
| 319 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivhd_11->length); |
| 320 | |
| 321 | /* Describe HPET */ |
| 322 | current_backup = current; |
| 323 | current = ivhd_describe_hpet(current); |
| 324 | ivhd_11->length += (current - current_backup); |
| 325 | |
| 326 | /* Describe IOAPICs */ |
| 327 | current_backup = current; |
| 328 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 329 | ivhd_11->length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 330 | |
| 331 | return current; |
| 332 | } |
| 333 | |
| 334 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 335 | { |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 336 | acpi_ivrs_t *ivrs_agesa; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 337 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 338 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 339 | struct device *nb_dev = pcidev_on_root(0, 0); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 340 | if (!nb_dev) { |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 341 | printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); |
| 342 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 343 | |
| 344 | return (unsigned long)ivrs; |
| 345 | } |
| 346 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 347 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 348 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 349 | if (!iommu_dev) { |
| 350 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 351 | |
| 352 | return (unsigned long)ivrs; |
| 353 | } |
| 354 | |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 355 | ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); |
| 356 | if (ivrs_agesa != NULL) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 357 | ivrs->iv_info = ivrs_agesa->iv_info; |
| 358 | ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 359 | ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 360 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 361 | /* BDF <bus>:00.2 */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 362 | ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 363 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 364 | ivrs->ivhd.capability_offset = 0x40; |
| 365 | ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 366 | ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 367 | ivrs->ivhd.pci_segment_group = 0x0000; |
| 368 | ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 369 | ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; |
| 370 | /* Enable EFR if supported */ |
| 371 | if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) |
| 372 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 373 | } else { |
| 374 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 375 | |
| 376 | return (unsigned long)ivrs; |
| 377 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 378 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 379 | /* |
| 380 | * Add all possible PCI devices on bus 0 that can generate transactions |
| 381 | * processed by IOMMU. Start with device 00:01.0 since IOMMU does not |
| 382 | * translate transactions generated by itself. |
| 383 | */ |
| 384 | current_backup = current; |
| 385 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 386 | ivrs->ivhd.length += (current - current_backup); |
| 387 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 388 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 389 | /* Describe HPET */ |
| 390 | current_backup = current; |
| 391 | current = ivhd_describe_hpet(current); |
| 392 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 393 | |
| 394 | /* Describe IOAPICs */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 395 | current_backup = current; |
| 396 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 397 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 398 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 399 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 400 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 401 | return current; |
| 402 | |
| 403 | return acpi_fill_ivrs11(current, ivrs_agesa); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 404 | } |
| 405 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 406 | static void northbridge_fill_ssdt_generator(const struct device *device) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 407 | { |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 408 | char pscope[] = "\\_SB.PCI0"; |
| 409 | |
| 410 | acpigen_write_scope(pscope); |
Felix Held | e345378 | 2023-04-20 13:06:08 +0200 | [diff] [blame] | 411 | acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); |
| 412 | |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 413 | /* |
| 414 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 415 | * here. |
| 416 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 417 | * slide 22ff. |
| 418 | * Shift value right by 20 bit to make it fit into 32bit, |
| 419 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 420 | */ |
Felix Held | 27af3e6 | 2023-04-22 05:59:52 +0200 | [diff] [blame] | 421 | acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 422 | acpigen_pop_len(); |
| 423 | } |
| 424 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 425 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 426 | unsigned long current, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 427 | acpi_rsdp_t *rsdp) |
| 428 | { |
| 429 | acpi_srat_t *srat; |
| 430 | acpi_slit_t *slit; |
| 431 | acpi_header_t *ssdt; |
| 432 | acpi_header_t *alib; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 433 | acpi_ivrs_t *ivrs; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 434 | |
| 435 | /* HEST */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 436 | current = ALIGN_UP(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 437 | acpi_write_hest((void *)current, acpi_fill_hest); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 438 | acpi_add_table(rsdp, (void *)current); |
| 439 | current += ((acpi_header_t *)current)->length; |
| 440 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 441 | /* IVRS */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 442 | current = ALIGN_UP(current, 8); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 443 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 444 | ivrs = (acpi_ivrs_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 445 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 446 | current += ivrs->header.length; |
| 447 | acpi_add_table(rsdp, ivrs); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 448 | |
| 449 | /* SRAT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 450 | current = ALIGN_UP(current, 8); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 451 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 452 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 453 | if (srat != NULL) { |
| 454 | memcpy((void *)current, srat, srat->header.length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 455 | srat = (acpi_srat_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 456 | current += srat->header.length; |
| 457 | acpi_add_table(rsdp, srat); |
| 458 | } else { |
| 459 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 460 | } |
| 461 | |
| 462 | /* SLIT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 463 | current = ALIGN_UP(current, 8); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 464 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 465 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 466 | if (slit != NULL) { |
| 467 | memcpy((void *)current, slit, slit->header.length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 468 | slit = (acpi_slit_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 469 | current += slit->header.length; |
| 470 | acpi_add_table(rsdp, slit); |
| 471 | } else { |
| 472 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 473 | } |
| 474 | |
| 475 | /* ALIB */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 476 | current = ALIGN_UP(current, 16); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 477 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 478 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 479 | if (alib != NULL) { |
| 480 | memcpy((void *)current, alib, alib->length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 481 | alib = (acpi_header_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 482 | current += alib->length; |
| 483 | acpi_add_table(rsdp, (void *)alib); |
| 484 | } |
| 485 | else { |
| 486 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 487 | } |
| 488 | |
| 489 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 490 | /* SSDT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 491 | current = ALIGN_UP(current, 16); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 492 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 493 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 494 | if (ssdt != NULL) { |
| 495 | memcpy((void *)current, ssdt, ssdt->length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 496 | ssdt = (acpi_header_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 497 | current += ssdt->length; |
| 498 | } |
| 499 | else { |
| 500 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 501 | } |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 502 | acpi_add_table(rsdp, ssdt); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 503 | |
| 504 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 505 | return current; |
| 506 | } |
| 507 | |
Felix Held | 7b9c647 | 2023-11-16 16:06:49 +0100 | [diff] [blame] | 508 | struct device_operations amd_pi_northbridge_ops = { |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 509 | .read_resources = nb_read_resources, |
Felix Held | b986e21 | 2023-12-16 00:58:09 +0100 | [diff] [blame] | 510 | .set_resources = pci_dev_set_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 511 | .enable_resources = pci_dev_enable_resources, |
| 512 | .init = northbridge_init, |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 513 | .ops_pci = &pci_dev_ops_pci, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 514 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 515 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 516 | }; |
| 517 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 518 | static void fam16_finalize(void *chip_info) |
| 519 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 520 | struct device *dev; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 521 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 522 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 523 | pci_write_config32(dev, 0xF8, 0); |
| 524 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 525 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 526 | /* |
| 527 | * Currently it is impossible to enable ACS with AGESA by setting the |
| 528 | * correct bit for AmdInitMid phase. AGESA code path does not call the |
| 529 | * right function that enables these functionalities. Disabled ACS |
| 530 | * result in multiple PCIe devices to be assigned to the same IOMMU |
| 531 | * group. Without IOMMU group separation the devices cannot be passed |
| 532 | * through independently. |
| 533 | */ |
| 534 | |
| 535 | /* Select GPP link core IO Link Strap Control register 0xB0 */ |
| 536 | pci_write_config32(dev, 0xE0, 0x014000B0); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 537 | |
| 538 | /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 539 | pci_or_config32(dev, 0xE4, PCIE_CAP_AER | PCIE_CAP_ACS); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 540 | |
| 541 | /* Select GPP link core Wrapper register 0x00 (undocumented) */ |
| 542 | pci_write_config32(dev, 0xE0, 0x01300000); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 543 | |
| 544 | /* |
| 545 | * Enable ACS capabilities straps including sub-items. From lspci it |
| 546 | * looks like these bits enable: Source Validation and Translation |
| 547 | * Blocking |
| 548 | */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 549 | pci_or_config32(dev, 0xE4, (BIT(24) | BIT(25) | BIT(26))); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 550 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 551 | /* disable No Snoop */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 552 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 553 | if (dev != NULL) { |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 554 | pci_and_config32(dev, 0x60, ~(1 << 11)); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 555 | } |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 556 | } |
| 557 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 558 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 559 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 560 | unsigned int hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 561 | int node_id; |
| 562 | }; |
| 563 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 564 | { |
| 565 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 566 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 567 | mem_hole.node_id = -1; |
Felix Held | a880720 | 2023-11-16 21:29:33 +0100 | [diff] [blame] | 568 | |
| 569 | resource_t basek, limitk; |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 570 | if (get_dram_base_limit(&basek, &limitk)) { // memory on this node |
Felix Held | 7a83ab7 | 2023-12-16 23:10:50 +0100 | [diff] [blame^] | 571 | u32 hole = pci_read_config32(DEV_PTR(ht_1), 0xf0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 572 | if (hole & 2) { // we find the hole |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 573 | mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; |
Felix Held | a880720 | 2023-11-16 21:29:33 +0100 | [diff] [blame] | 574 | mem_hole.node_id = 0; // record the node No with hole |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 575 | } |
| 576 | } |
| 577 | return mem_hole; |
| 578 | } |
| 579 | #endif |
| 580 | |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 581 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 582 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 583 | unsigned long mmio_basek; |
Felix Held | dcbb1e8 | 2023-12-17 18:20:01 +0100 | [diff] [blame] | 584 | unsigned long idx = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 585 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 586 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 587 | #endif |
Felix Held | 3f234f8 | 2023-12-17 18:38:08 +0100 | [diff] [blame] | 588 | resource_t basek = 0; |
| 589 | resource_t limitk = 0; |
| 590 | resource_t sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 591 | |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 592 | pci_domain_read_resources(dev); |
| 593 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 594 | /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ |
Felix Held | 5e9afe7 | 2023-04-20 12:55:55 +0200 | [diff] [blame] | 595 | mmio_basek = get_top_of_mem_below_4gb() >> 10; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 596 | |
| 597 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 598 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 599 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 600 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 601 | * otherwise We reset the hole to the mmio_basek |
| 602 | */ |
| 603 | |
| 604 | mem_hole = get_hw_mem_hole_info(); |
| 605 | |
| 606 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 607 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 608 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 609 | } |
| 610 | #endif |
| 611 | |
Felix Held | 3f234f8 | 2023-12-17 18:38:08 +0100 | [diff] [blame] | 612 | get_dram_base_limit(&basek, &limitk); |
| 613 | sizek = limitk - basek; |
| 614 | |
| 615 | printk(BIOS_DEBUG, "basek=%08llx, limitk=%08llx, sizek=%08llx,\n", |
| 616 | basek, limitk, sizek); |
| 617 | |
| 618 | /* See if we need a hole from 0xa0000 (640K) to 0xfffff (1024K) */ |
| 619 | if (basek < 640 && sizek > 1024) { |
| 620 | ram_resource_kb(dev, idx++, basek, 640 - basek); |
| 621 | basek = 1024; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 622 | sizek = limitk - basek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 623 | } |
| 624 | |
Felix Held | 3f234f8 | 2023-12-17 18:38:08 +0100 | [diff] [blame] | 625 | printk(BIOS_DEBUG, "basek=%08llx, limitk=%08llx, sizek=%08llx,\n", |
| 626 | basek, limitk, sizek); |
| 627 | |
| 628 | /* split the region to accommodate pci memory space */ |
| 629 | if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { |
| 630 | if (basek <= mmio_basek) { |
| 631 | unsigned int pre_sizek; |
| 632 | pre_sizek = mmio_basek - basek; |
| 633 | if (pre_sizek > 0) { |
| 634 | ram_resource_kb(dev, idx++, basek, pre_sizek); |
| 635 | sizek -= pre_sizek; |
| 636 | } |
| 637 | basek = mmio_basek; |
| 638 | } |
| 639 | if ((basek + sizek) <= 4 * 1024 * 1024) { |
| 640 | sizek = 0; |
| 641 | } else { |
| 642 | uint64_t topmem2 = get_top_of_mem_above_4gb(); |
| 643 | basek = 4 * 1024 * 1024; |
| 644 | sizek = topmem2 / 1024 - basek; |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | ram_resource_kb(dev, idx++, basek, sizek); |
| 649 | printk(BIOS_DEBUG, "mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 650 | mmio_basek, basek, limitk); |
| 651 | |
Felix Held | dcbb1e8 | 2023-12-17 18:20:01 +0100 | [diff] [blame] | 652 | add_uma_resource_below_tolm(dev, idx++); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 653 | } |
| 654 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 655 | static const char *domain_acpi_name(const struct device *dev) |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 656 | { |
| 657 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 658 | return "PCI0"; |
| 659 | |
| 660 | return NULL; |
| 661 | } |
| 662 | |
Felix Held | 8ccd314 | 2023-11-16 00:58:30 +0100 | [diff] [blame] | 663 | struct device_operations amd_fam16_mod30_pci_domain_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 664 | .read_resources = domain_read_resources, |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 665 | .set_resources = pci_domain_set_resources, |
Arthur Heymans | 0b0113f | 2023-08-31 17:09:28 +0200 | [diff] [blame] | 666 | .scan_bus = pci_host_bridge_scan_bus, |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 667 | .acpi_name = domain_acpi_name, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 668 | }; |
| 669 | |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 670 | void mp_init_cpus(struct bus *cpu_bus) |
| 671 | { |
Arthur Heymans | 4fcaccf | 2022-06-02 13:17:37 +0200 | [diff] [blame] | 672 | extern const struct mp_ops amd_mp_ops_no_smm; |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 673 | /* TODO: Handle mp_init_with_smm failure? */ |
Arthur Heymans | 4fcaccf | 2022-06-02 13:17:37 +0200 | [diff] [blame] | 674 | mp_init_with_smm(cpu_bus, &amd_mp_ops_no_smm); |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 675 | |
| 676 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
| 677 | mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, |
| 678 | MTRR_TYPE_WRPROT); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 679 | } |
| 680 | |
Felix Held | c391bff | 2023-02-16 19:38:49 +0100 | [diff] [blame] | 681 | void generate_cpu_entries(const struct device *device) |
| 682 | { |
| 683 | int cpu; |
| 684 | const int cores = get_cpu_count(); |
| 685 | |
| 686 | printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); |
| 687 | |
| 688 | /* Generate \_SB.Pxxx */ |
| 689 | for (cpu = 0; cpu < cores; cpu++) { |
| 690 | acpigen_write_processor_device(cpu); |
| 691 | acpigen_write_processor_device_end(); |
| 692 | } |
| 693 | } |
| 694 | |
Felix Held | 8ccd314 | 2023-11-16 00:58:30 +0100 | [diff] [blame] | 695 | struct device_operations amd_fam16_mod30_cpu_bus_ops = { |
Felix Held | c391bff | 2023-02-16 19:38:49 +0100 | [diff] [blame] | 696 | .read_resources = noop_read_resources, |
| 697 | .set_resources = noop_set_resources, |
| 698 | .init = mp_cpu_bus_init, |
| 699 | .acpi_fill_ssdt = generate_cpu_entries, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 700 | }; |
| 701 | |
Felix Held | 1952d13 | 2023-11-16 00:54:30 +0100 | [diff] [blame] | 702 | struct chip_operations northbridge_amd_pi_00730F01_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 703 | CHIP_NAME("AMD FAM16 Root Complex") |
Felix Held | 1952d13 | 2023-11-16 00:54:30 +0100 | [diff] [blame] | 704 | .final = fam16_finalize, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 705 | }; |
| 706 | |
| 707 | /********************************************************************* |
| 708 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 709 | *********************************************************************/ |
| 710 | u32 map_oprom_vendev(u32 vendev) |
| 711 | { |
| 712 | u32 new_vendev; |
| 713 | new_vendev = |
| 714 | ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; |
| 715 | |
| 716 | if (vendev != new_vendev) |
| 717 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 718 | |
| 719 | return new_vendev; |
| 720 | } |