Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 2 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
| 7 | #include <acpi/acpi_ivrs.h> |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Elyes HAOUAS | 146d0c2 | 2020-07-22 11:47:08 +0200 | [diff] [blame] | 9 | #include <types.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 13 | #include <string.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 14 | #include <stdlib.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 15 | #include <lib.h> |
| 16 | #include <cpu/cpu.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 17 | #include <Porting.h> |
| 18 | #include <AGESA.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 19 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 20 | #include <cpu/x86/lapic.h> |
| 21 | #include <cpu/amd/msr.h> |
| 22 | #include <cpu/amd/mtrr.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 23 | #include <acpi/acpigen.h> |
Angel Pons | ec5cf15 | 2020-11-10 20:42:07 +0100 | [diff] [blame] | 24 | #include <northbridge/amd/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 25 | #include <northbridge/amd/agesa/agesa_helper.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 26 | #include <southbridge/amd/pi/hudson/pci_devs.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 27 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 28 | #define MAX_NODE_NUMS MAX_NODES |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 29 | #define PCIE_CAP_AER BIT(5) |
| 30 | #define PCIE_CAP_ACS BIT(6) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 31 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 32 | static unsigned int node_nums; |
| 33 | static unsigned int sblink; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 34 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 35 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 36 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 37 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 38 | static unsigned int fx_devs = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 39 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 40 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 41 | u32 io_min, u32 io_max) |
| 42 | { |
| 43 | u32 i; |
| 44 | u32 tempreg; |
| 45 | /* io range allocation */ |
| 46 | tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 47 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 48 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 49 | tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 50 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 51 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 52 | } |
| 53 | |
| 54 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) |
| 55 | { |
| 56 | u32 i; |
| 57 | u32 tempreg; |
| 58 | /* io range allocation */ |
| 59 | tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 60 | for (i = 0; i < nodes; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 61 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 62 | tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 63 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 64 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 65 | } |
| 66 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 67 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 68 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 69 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | static void get_fx_devs(void) |
| 73 | { |
| 74 | int i; |
| 75 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 76 | __f0_dev[i] = get_node_pci(i, 0); |
| 77 | __f1_dev[i] = get_node_pci(i, 1); |
| 78 | __f2_dev[i] = get_node_pci(i, 2); |
| 79 | __f4_dev[i] = get_node_pci(i, 4); |
| 80 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 81 | fx_devs = i+1; |
| 82 | } |
| 83 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 84 | die("Cannot find 0:0x18.[0|1]\n"); |
| 85 | } |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 86 | printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 87 | } |
| 88 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 89 | static u32 f1_read_config32(unsigned int reg) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 90 | { |
| 91 | if (fx_devs == 0) |
| 92 | get_fx_devs(); |
| 93 | return pci_read_config32(__f1_dev[0], reg); |
| 94 | } |
| 95 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 96 | static void f1_write_config32(unsigned int reg, u32 value) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 97 | { |
| 98 | int i; |
| 99 | if (fx_devs == 0) |
| 100 | get_fx_devs(); |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 101 | for (i = 0; i < fx_devs; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 102 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 103 | dev = __f1_dev[i]; |
| 104 | if (dev && dev->enabled) { |
| 105 | pci_write_config32(dev, reg, value); |
| 106 | } |
| 107 | } |
| 108 | } |
| 109 | |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame^] | 110 | static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) |
| 111 | { |
| 112 | u32 temp; |
| 113 | |
| 114 | if (fx_devs == 0) |
| 115 | get_fx_devs(); |
| 116 | |
| 117 | |
| 118 | temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 119 | if (!(temp & 1)) |
| 120 | return 0; // this memory range is not enabled |
| 121 | /* |
| 122 | * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits |
| 123 | * for physical address and the convert to KiB by shifting 10 bits left |
| 124 | */ |
| 125 | *basek = ((temp & 0xffff0000)) >> (10 - 8); |
| 126 | /* |
| 127 | * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but |
| 128 | * ORed with 0xffff to get real limit before shifting. |
| 129 | */ |
| 130 | temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 131 | *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); |
| 132 | *limitk += 1; // round up last byte |
| 133 | |
| 134 | return 1; |
| 135 | } |
| 136 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 137 | static u32 amdfam16_nodeid(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 138 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 139 | return (dev->path.pci.devfn >> 3) - DEV_CDB; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 143 | { |
| 144 | u32 val; |
| 145 | |
| 146 | val = 1 | (nodeid<<4) | (linkn<<12); |
| 147 | /* it will routing |
| 148 | * (1)mmio 0xa0000:0xbffff |
| 149 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 150 | */ |
| 151 | f1_write_config32(0xf4, val); |
| 152 | |
| 153 | } |
| 154 | |
| 155 | /** |
| 156 | * @return |
Elyes HAOUAS | 99b075a | 2019-12-30 14:29:31 +0100 | [diff] [blame] | 157 | * @retval 2 resource does not exist, usable |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 158 | * @retval 0 resource exists, not usable |
| 159 | * @retval 1 resource exist, resource has been allocated before |
| 160 | */ |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 161 | static int reg_useable(unsigned int reg, struct device *goal_dev, |
| 162 | unsigned int goal_nodeid, unsigned int goal_link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 163 | { |
| 164 | struct resource *res; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 165 | unsigned int nodeid, link = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 166 | int result; |
| 167 | res = 0; |
| 168 | for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 169 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 170 | dev = __f0_dev[nodeid]; |
| 171 | if (!dev) |
| 172 | continue; |
| 173 | for (link = 0; !res && (link < 8); link++) { |
| 174 | res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 175 | } |
| 176 | } |
| 177 | result = 2; |
| 178 | if (res) { |
| 179 | result = 0; |
| 180 | if ((goal_link == (link - 1)) && |
| 181 | (goal_nodeid == (nodeid - 1)) && |
| 182 | (res->flags <= 1)) { |
| 183 | result = 1; |
| 184 | } |
| 185 | } |
| 186 | return result; |
| 187 | } |
| 188 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 189 | static struct resource *amdfam16_find_iopair(struct device *dev, |
| 190 | unsigned int nodeid, unsigned int link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 191 | { |
| 192 | struct resource *resource; |
| 193 | u32 free_reg, reg; |
| 194 | resource = 0; |
| 195 | free_reg = 0; |
| 196 | for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { |
| 197 | int result; |
| 198 | result = reg_useable(reg, dev, nodeid, link); |
| 199 | if (result == 1) { |
| 200 | /* I have been allocated this one */ |
| 201 | break; |
| 202 | } |
| 203 | else if (result > 1) { |
| 204 | /* I have a free register pair */ |
| 205 | free_reg = reg; |
| 206 | } |
| 207 | } |
| 208 | if (reg > 0xd8) { |
| 209 | reg = free_reg; // if no free, the free_reg still be 0 |
| 210 | } |
| 211 | |
| 212 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 213 | |
| 214 | return resource; |
| 215 | } |
| 216 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 217 | static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 218 | { |
| 219 | struct resource *resource; |
| 220 | u32 free_reg, reg; |
| 221 | resource = 0; |
| 222 | free_reg = 0; |
| 223 | for (reg = 0x80; reg <= 0xb8; reg += 0x8) { |
| 224 | int result; |
| 225 | result = reg_useable(reg, dev, nodeid, link); |
| 226 | if (result == 1) { |
| 227 | /* I have been allocated this one */ |
| 228 | break; |
| 229 | } |
| 230 | else if (result > 1) { |
| 231 | /* I have a free register pair */ |
| 232 | free_reg = reg; |
| 233 | } |
| 234 | } |
| 235 | if (reg > 0xb8) { |
| 236 | reg = free_reg; |
| 237 | } |
| 238 | |
| 239 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 240 | return resource; |
| 241 | } |
| 242 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 243 | static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 244 | { |
| 245 | struct resource *resource; |
| 246 | |
| 247 | /* Initialize the io space constraints on the current bus */ |
| 248 | resource = amdfam16_find_iopair(dev, nodeid, link); |
| 249 | if (resource) { |
| 250 | u32 align; |
| 251 | align = log2(HT_IO_HOST_ALIGN); |
| 252 | resource->base = 0; |
| 253 | resource->size = 0; |
| 254 | resource->align = align; |
| 255 | resource->gran = align; |
| 256 | resource->limit = 0xffffUL; |
| 257 | resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; |
| 258 | } |
| 259 | |
| 260 | /* Initialize the prefetchable memory constraints on the current bus */ |
| 261 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 262 | if (resource) { |
| 263 | resource->base = 0; |
| 264 | resource->size = 0; |
| 265 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 266 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 267 | resource->limit = 0xffffffffffULL; |
| 268 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 269 | resource->flags |= IORESOURCE_BRIDGE; |
| 270 | } |
| 271 | |
| 272 | /* Initialize the memory constraints on the current bus */ |
| 273 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 274 | if (resource) { |
| 275 | resource->base = 0; |
| 276 | resource->size = 0; |
| 277 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 278 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 279 | resource->limit = 0xffffffffffULL; |
| 280 | resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; |
| 281 | } |
| 282 | |
| 283 | } |
| 284 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 285 | static void read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 286 | { |
| 287 | u32 nodeid; |
| 288 | struct bus *link; |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 289 | struct resource *res; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 290 | |
| 291 | nodeid = amdfam16_nodeid(dev); |
| 292 | for (link = dev->link_list; link; link = link->next) { |
| 293 | if (link->children) { |
| 294 | amdfam16_link_read_bases(dev, nodeid, link->link_num); |
| 295 | } |
| 296 | } |
Kyösti Mälkki | 5d49038 | 2015-05-27 07:58:22 +0300 | [diff] [blame] | 297 | |
| 298 | /* |
| 299 | * This MMCONF resource must be reserved in the PCI domain. |
| 300 | * It is not honored by the coreboot resource allocator if it is in |
| 301 | * the CPU_CLUSTER. |
| 302 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 303 | mmconf_resource(dev, MMIO_CONF_BASE); |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 304 | |
| 305 | /* NB IOAPIC2 resource */ |
| 306 | res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ |
| 307 | res->base = IO_APIC2_ADDR; |
| 308 | res->size = 0x00001000; |
| 309 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 310 | } |
| 311 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 312 | static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 313 | { |
| 314 | resource_t rbase, rend; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 315 | unsigned int reg, link_num; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 316 | char buf[50]; |
| 317 | |
| 318 | /* Make certain the resource has actually been set */ |
| 319 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
| 320 | return; |
| 321 | } |
| 322 | |
| 323 | /* If I have already stored this resource don't worry about it */ |
| 324 | if (resource->flags & IORESOURCE_STORED) { |
| 325 | return; |
| 326 | } |
| 327 | |
| 328 | /* Only handle PCI memory and IO resources */ |
| 329 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 330 | return; |
| 331 | |
| 332 | /* Ensure I am actually looking at a resource of function 1 */ |
| 333 | if ((resource->index & 0xffff) < 0x1000) { |
| 334 | return; |
| 335 | } |
| 336 | /* Get the base address */ |
| 337 | rbase = resource->base; |
| 338 | |
| 339 | /* Get the limit (rounded up) */ |
| 340 | rend = resource_end(resource); |
| 341 | |
| 342 | /* Get the register and link */ |
| 343 | reg = resource->index & 0xfff; // 4k |
| 344 | link_num = IOINDEX_LINK(resource->index); |
| 345 | |
| 346 | if (resource->flags & IORESOURCE_IO) { |
| 347 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
| 348 | } |
| 349 | else if (resource->flags & IORESOURCE_MEM) { |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 350 | set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 351 | } |
| 352 | resource->flags |= IORESOURCE_STORED; |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 353 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 354 | nodeid, link_num); |
| 355 | report_resource_stored(dev, resource, buf); |
| 356 | } |
| 357 | |
| 358 | /** |
| 359 | * I tried to reuse the resource allocation code in set_resource() |
| 360 | * but it is too difficult to deal with the resource allocation magic. |
| 361 | */ |
| 362 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 363 | static void create_vga_resource(struct device *dev, unsigned int nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 364 | { |
| 365 | struct bus *link; |
| 366 | |
| 367 | /* find out which link the VGA card is connected, |
| 368 | * we only deal with the 'first' vga card */ |
| 369 | for (link = dev->link_list; link; link = link->next) { |
| 370 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 371 | #if CONFIG(MULTIPLE_VGA_ADAPTERS) |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 372 | extern struct device *vga_pri; // the primary vga device, defined in device.c |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 373 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 374 | link->secondary,link->subordinate); |
| 375 | /* We need to make sure the vga_pri is under the link */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 376 | if ((vga_pri->bus->secondary >= link->secondary) && |
| 377 | (vga_pri->bus->secondary <= link->subordinate)) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 378 | #endif |
| 379 | break; |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | /* no VGA card installed */ |
| 384 | if (link == NULL) |
| 385 | return; |
| 386 | |
| 387 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 388 | set_vga_enable_reg(nodeid, sblink); |
| 389 | } |
| 390 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 391 | static void set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 392 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 393 | unsigned int nodeid; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 394 | struct bus *bus; |
| 395 | struct resource *res; |
| 396 | |
| 397 | /* Find the nodeid */ |
| 398 | nodeid = amdfam16_nodeid(dev); |
| 399 | |
| 400 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 401 | |
| 402 | /* Set each resource we have found */ |
| 403 | for (res = dev->resource_list; res; res = res->next) { |
| 404 | set_resource(dev, res, nodeid); |
| 405 | } |
| 406 | |
| 407 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 408 | if (bus->children) { |
| 409 | assign_resources(bus); |
| 410 | } |
| 411 | } |
| 412 | } |
| 413 | |
| 414 | static void northbridge_init(struct device *dev) |
| 415 | { |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 416 | setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 417 | } |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 418 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 419 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 420 | { |
| 421 | void *addr, *current; |
| 422 | |
| 423 | /* Skip the HEST header. */ |
| 424 | current = (void *)(hest + 1); |
| 425 | |
| 426 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 427 | if (addr != NULL) |
| 428 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 429 | |
| 430 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 431 | if (addr != NULL) |
| 432 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 433 | |
| 434 | return (unsigned long)current; |
| 435 | } |
| 436 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 437 | unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 438 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 439 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 440 | current = ALIGN_UP(current, 8); |
| 441 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 442 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 443 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 444 | ivhd_ioapic->reserved = 0x0000; |
| 445 | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 446 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 447 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
| 448 | ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ |
| 449 | ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 450 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 451 | current += sizeof(ivrs_ivhd_special_t); |
| 452 | |
| 453 | ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
| 454 | |
| 455 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 456 | ivhd_ioapic->reserved = 0x0000; |
| 457 | ivhd_ioapic->dte_setting = 0x00; |
| 458 | ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ |
| 459 | ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); |
| 460 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 461 | current += sizeof(ivrs_ivhd_special_t); |
| 462 | |
| 463 | return current; |
| 464 | } |
| 465 | |
| 466 | static unsigned long ivhd_describe_hpet(unsigned long current) |
| 467 | { |
| 468 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 469 | current = ALIGN_UP(current, 8); |
| 470 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
| 471 | |
| 472 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 473 | ivhd_hpet->reserved = 0x0000; |
| 474 | ivhd_hpet->dte_setting = 0x00; |
| 475 | ivhd_hpet->handle = 0x00; |
| 476 | ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 477 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 478 | current += sizeof(ivrs_ivhd_special_t); |
| 479 | |
| 480 | return current; |
| 481 | } |
| 482 | |
| 483 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 484 | uint16_t end_devid, uint8_t setting) |
| 485 | { |
| 486 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 487 | current = ALIGN_UP(current, 4); |
| 488 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 489 | |
| 490 | /* Create the start range IVHD entry */ |
| 491 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 492 | ivhd_range->dev_id = start_devid; |
| 493 | ivhd_range->dte_setting = setting; |
| 494 | current += sizeof(ivrs_ivhd_generic_t); |
| 495 | |
| 496 | /* Create the end range IVHD entry */ |
| 497 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 498 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 499 | ivhd_range->dev_id = end_devid; |
| 500 | ivhd_range->dte_setting = setting; |
| 501 | current += sizeof(ivrs_ivhd_generic_t); |
| 502 | |
| 503 | return current; |
| 504 | } |
| 505 | |
| 506 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 507 | unsigned long *current, uint8_t type, uint8_t data) |
| 508 | { |
| 509 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 510 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 511 | *current = ALIGN_UP(*current, 4); |
| 512 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 513 | |
| 514 | ivhd_entry->type = type; |
| 515 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 516 | ivhd_entry->dte_setting = data; |
| 517 | *current += sizeof(ivrs_ivhd_generic_t); |
| 518 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 519 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 520 | *current = ALIGN_UP(*current, 8); |
| 521 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 522 | |
| 523 | ivhd_entry->type = type; |
| 524 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 525 | ivhd_entry->dte_setting = data; |
| 526 | ivhd_entry->reserved1 = 0; |
| 527 | ivhd_entry->reserved2 = 0; |
| 528 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 529 | (parent->bus->secondary << 8); |
| 530 | *current += sizeof(ivrs_ivhd_alias_t); |
| 531 | } |
| 532 | |
| 533 | return *current; |
| 534 | } |
| 535 | |
| 536 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
| 537 | unsigned long *current, uint16_t *ivhd_length) |
| 538 | { |
| 539 | unsigned int header_type, is_pcie; |
| 540 | unsigned long current_backup; |
| 541 | |
| 542 | header_type = dev->hdr_type & 0x7f; |
| 543 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 544 | |
| 545 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 546 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 547 | /* Device or Bridge is PCIe */ |
| 548 | current_backup = *current; |
| 549 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
| 550 | *ivhd_length += (*current - current_backup); |
| 551 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 552 | /* Device is legacy PCI or PCI-X */ |
| 553 | current_backup = *current; |
| 554 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
| 555 | *ivhd_length += (*current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 556 | } |
| 557 | } |
| 558 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 559 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 560 | unsigned int depth, int linknum, int8_t *root_level, |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 561 | unsigned long *current, uint16_t *ivhd_length) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 562 | { |
| 563 | struct device *sibling; |
| 564 | struct bus *link; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 565 | |
| 566 | if (!root_level) { |
| 567 | root_level = malloc(sizeof(int8_t)); |
| 568 | *root_level = -1; |
| 569 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 570 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 571 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 572 | |
| 573 | if ((dev->bus->secondary == 0x0) && |
| 574 | (dev->path.pci.devfn == 0x0)) |
| 575 | *root_level = depth; |
| 576 | |
| 577 | if ((*root_level != -1) && (dev->enabled)) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 578 | if (depth != *root_level) |
| 579 | ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 580 | } |
| 581 | } |
| 582 | |
| 583 | for (link = dev->link_list; link; link = link->next) |
| 584 | for (sibling = link->children; sibling; sibling = |
| 585 | sibling->sibling) |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 586 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
| 587 | current, ivhd_length); |
| 588 | |
| 589 | free(root_level); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 590 | } |
| 591 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 592 | #define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) |
| 593 | #define EFR_SUPPORT BIT(27) |
| 594 | |
| 595 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 596 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 597 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 598 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 599 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 600 | /* |
| 601 | * These devices should be already found by previous function. |
| 602 | * Do not perform NULL checks. |
| 603 | */ |
| 604 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 605 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 606 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 607 | /* |
| 608 | * In order to utilize all features, firmware should expose type 11h |
| 609 | * IVHD which supersedes the type 10h. |
| 610 | */ |
| 611 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 612 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 613 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 614 | /* Enable EFR */ |
| 615 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 616 | /* For type 11h bits 6 and 7 are reserved */ |
| 617 | ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; |
| 618 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 619 | /* BDF <bus>:00.2 */ |
| 620 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 621 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
| 622 | ivhd_11->capability_offset = 0x40; |
| 623 | ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 624 | ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
| 625 | ivhd_11->pci_segment_group = 0x0000; |
| 626 | ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 627 | ivhd_11->iommu_attributes.perf_counters = |
| 628 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; |
| 629 | ivhd_11->iommu_attributes.perf_counter_banks = |
| 630 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; |
| 631 | ivhd_11->iommu_attributes.msi_num_ppr = |
| 632 | (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 633 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 634 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { |
| 635 | ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); |
| 636 | ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); |
| 637 | } |
| 638 | |
| 639 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 640 | |
| 641 | /* Now repeat all the device entries from type 10h */ |
| 642 | current_backup = current; |
| 643 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 644 | ivhd_11->length += (current - current_backup); |
| 645 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivhd_11->length); |
| 646 | |
| 647 | /* Describe HPET */ |
| 648 | current_backup = current; |
| 649 | current = ivhd_describe_hpet(current); |
| 650 | ivhd_11->length += (current - current_backup); |
| 651 | |
| 652 | /* Describe IOAPICs */ |
| 653 | current_backup = current; |
| 654 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 655 | ivhd_11->length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 656 | |
| 657 | return current; |
| 658 | } |
| 659 | |
| 660 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 661 | { |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 662 | acpi_ivrs_t *ivrs_agesa; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 663 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 664 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 665 | struct device *nb_dev = pcidev_on_root(0, 0); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 666 | if (!nb_dev) { |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 667 | printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); |
| 668 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 669 | |
| 670 | return (unsigned long)ivrs; |
| 671 | } |
| 672 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 673 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 674 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 675 | if (!iommu_dev) { |
| 676 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 677 | |
| 678 | return (unsigned long)ivrs; |
| 679 | } |
| 680 | |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 681 | ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); |
| 682 | if (ivrs_agesa != NULL) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 683 | ivrs->iv_info = ivrs_agesa->iv_info; |
| 684 | ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 685 | ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 686 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 687 | /* BDF <bus>:00.2 */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 688 | ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 689 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 690 | ivrs->ivhd.capability_offset = 0x40; |
| 691 | ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 692 | ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 693 | ivrs->ivhd.pci_segment_group = 0x0000; |
| 694 | ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 695 | ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; |
| 696 | /* Enable EFR if supported */ |
| 697 | if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) |
| 698 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 699 | } else { |
| 700 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 701 | |
| 702 | return (unsigned long)ivrs; |
| 703 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 704 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 705 | /* |
| 706 | * Add all possible PCI devices on bus 0 that can generate transactions |
| 707 | * processed by IOMMU. Start with device 00:01.0 since IOMMU does not |
| 708 | * translate transactions generated by itself. |
| 709 | */ |
| 710 | current_backup = current; |
| 711 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 712 | ivrs->ivhd.length += (current - current_backup); |
| 713 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 714 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 715 | /* Describe HPET */ |
| 716 | current_backup = current; |
| 717 | current = ivhd_describe_hpet(current); |
| 718 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 719 | |
| 720 | /* Describe IOAPICs */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 721 | current_backup = current; |
| 722 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 723 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 724 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 725 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 726 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 727 | return current; |
| 728 | |
| 729 | return acpi_fill_ivrs11(current, ivrs_agesa); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 730 | } |
| 731 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 732 | static void northbridge_fill_ssdt_generator(const struct device *device) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 733 | { |
| 734 | msr_t msr; |
| 735 | char pscope[] = "\\_SB.PCI0"; |
| 736 | |
| 737 | acpigen_write_scope(pscope); |
| 738 | msr = rdmsr(TOP_MEM); |
| 739 | acpigen_write_name_dword("TOM1", msr.lo); |
| 740 | msr = rdmsr(TOP_MEM2); |
| 741 | /* |
| 742 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 743 | * here. |
| 744 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 745 | * slide 22ff. |
| 746 | * Shift value right by 20 bit to make it fit into 32bit, |
| 747 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 748 | */ |
| 749 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 750 | acpigen_pop_len(); |
| 751 | } |
| 752 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 753 | static void patch_ssdt_processor_scope(acpi_header_t *ssdt) |
| 754 | { |
| 755 | unsigned int len = ssdt->length - sizeof(acpi_header_t); |
| 756 | unsigned int i; |
| 757 | |
| 758 | for (i = sizeof(acpi_header_t); i < len; i++) { |
| 759 | /* Search for _PR_ scope and replace it with _SB_ */ |
| 760 | if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) |
| 761 | *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; |
| 762 | } |
| 763 | /* Recalculate checksum */ |
| 764 | ssdt->checksum = 0; |
| 765 | ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); |
| 766 | } |
| 767 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 768 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 769 | unsigned long current, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 770 | acpi_rsdp_t *rsdp) |
| 771 | { |
| 772 | acpi_srat_t *srat; |
| 773 | acpi_slit_t *slit; |
| 774 | acpi_header_t *ssdt; |
| 775 | acpi_header_t *alib; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 776 | acpi_ivrs_t *ivrs; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 777 | |
| 778 | /* HEST */ |
| 779 | current = ALIGN(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 780 | acpi_write_hest((void *)current, acpi_fill_hest); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 781 | acpi_add_table(rsdp, (void *)current); |
| 782 | current += ((acpi_header_t *)current)->length; |
| 783 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 784 | /* IVRS */ |
| 785 | current = ALIGN(current, 8); |
| 786 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 787 | ivrs = (acpi_ivrs_t *) current; |
| 788 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 789 | current += ivrs->header.length; |
| 790 | acpi_add_table(rsdp, ivrs); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 791 | |
| 792 | /* SRAT */ |
| 793 | current = ALIGN(current, 8); |
| 794 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 795 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 796 | if (srat != NULL) { |
| 797 | memcpy((void *)current, srat, srat->header.length); |
| 798 | srat = (acpi_srat_t *) current; |
| 799 | current += srat->header.length; |
| 800 | acpi_add_table(rsdp, srat); |
| 801 | } else { |
| 802 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 803 | } |
| 804 | |
| 805 | /* SLIT */ |
| 806 | current = ALIGN(current, 8); |
| 807 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 808 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 809 | if (slit != NULL) { |
| 810 | memcpy((void *)current, slit, slit->header.length); |
| 811 | slit = (acpi_slit_t *) current; |
| 812 | current += slit->header.length; |
| 813 | acpi_add_table(rsdp, slit); |
| 814 | } else { |
| 815 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 816 | } |
| 817 | |
| 818 | /* ALIB */ |
| 819 | current = ALIGN(current, 16); |
| 820 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 821 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 822 | if (alib != NULL) { |
| 823 | memcpy((void *)current, alib, alib->length); |
| 824 | alib = (acpi_header_t *) current; |
| 825 | current += alib->length; |
| 826 | acpi_add_table(rsdp, (void *)alib); |
| 827 | } |
| 828 | else { |
| 829 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 830 | } |
| 831 | |
| 832 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 833 | /* SSDT */ |
| 834 | current = ALIGN(current, 16); |
| 835 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
| 836 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 837 | if (ssdt != NULL) { |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 838 | patch_ssdt_processor_scope(ssdt); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 839 | memcpy((void *)current, ssdt, ssdt->length); |
| 840 | ssdt = (acpi_header_t *) current; |
| 841 | current += ssdt->length; |
| 842 | } |
| 843 | else { |
| 844 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 845 | } |
| 846 | acpi_add_table(rsdp,ssdt); |
| 847 | |
| 848 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 849 | return current; |
| 850 | } |
| 851 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 852 | static struct device_operations northbridge_operations = { |
| 853 | .read_resources = read_resources, |
| 854 | .set_resources = set_resources, |
| 855 | .enable_resources = pci_dev_enable_resources, |
| 856 | .init = northbridge_init, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 857 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 858 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 859 | }; |
| 860 | |
| 861 | static const struct pci_driver family16_northbridge __pci_driver = { |
| 862 | .ops = &northbridge_operations, |
| 863 | .vendor = PCI_VENDOR_ID_AMD, |
Marshall Dawson | 463f46e | 2016-10-14 20:46:08 -0600 | [diff] [blame] | 864 | .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 865 | }; |
| 866 | |
| 867 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 868 | .ops = &northbridge_operations, |
| 869 | .vendor = PCI_VENDOR_ID_AMD, |
| 870 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 871 | }; |
| 872 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 873 | static void fam16_finalize(void *chip_info) |
| 874 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 875 | struct device *dev; |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 876 | u32 value; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 877 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 878 | pci_write_config32(dev, 0xF8, 0); |
| 879 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 880 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 881 | /* |
| 882 | * Currently it is impossible to enable ACS with AGESA by setting the |
| 883 | * correct bit for AmdInitMid phase. AGESA code path does not call the |
| 884 | * right function that enables these functionalities. Disabled ACS |
| 885 | * result in multiple PCIe devices to be assigned to the same IOMMU |
| 886 | * group. Without IOMMU group separation the devices cannot be passed |
| 887 | * through independently. |
| 888 | */ |
| 889 | |
| 890 | /* Select GPP link core IO Link Strap Control register 0xB0 */ |
| 891 | pci_write_config32(dev, 0xE0, 0x014000B0); |
| 892 | value = pci_read_config32(dev, 0xE4); |
| 893 | |
| 894 | /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ |
| 895 | value |= PCIE_CAP_AER | PCIE_CAP_ACS; |
| 896 | pci_write_config32(dev, 0xE4, value); |
| 897 | |
| 898 | /* Select GPP link core Wrapper register 0x00 (undocumented) */ |
| 899 | pci_write_config32(dev, 0xE0, 0x01300000); |
| 900 | value = pci_read_config32(dev, 0xE4); |
| 901 | |
| 902 | /* |
| 903 | * Enable ACS capabilities straps including sub-items. From lspci it |
| 904 | * looks like these bits enable: Source Validation and Translation |
| 905 | * Blocking |
| 906 | */ |
| 907 | value |= (BIT(24) | BIT(25) | BIT(26)); |
| 908 | pci_write_config32(dev, 0xE4, value); |
| 909 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 910 | /* disable No Snoop */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 911 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 912 | if (dev != NULL) { |
| 913 | value = pci_read_config32(dev, 0x60); |
| 914 | value &= ~(1 << 11); |
| 915 | pci_write_config32(dev, 0x60, value); |
| 916 | } |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 917 | } |
| 918 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 919 | struct chip_operations northbridge_amd_pi_00730F01_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 920 | CHIP_NAME("AMD FAM16 Northbridge") |
| 921 | .enable_dev = 0, |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 922 | .final = fam16_finalize, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 923 | }; |
| 924 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 925 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 926 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 927 | unsigned int reg; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 928 | |
| 929 | /* Find the already assigned resource pairs */ |
| 930 | get_fx_devs(); |
| 931 | for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { |
| 932 | u32 base, limit; |
| 933 | base = f1_read_config32(reg); |
| 934 | limit = f1_read_config32(reg + 0x04); |
| 935 | /* Is this register allocated? */ |
| 936 | if ((base & 3) != 0) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 937 | unsigned int nodeid, reg_link; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 938 | struct device *reg_dev; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 939 | if (reg < 0xc0) { // mmio |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 940 | nodeid = (limit & 0xf) + (base&0x30); |
| 941 | } else { // io |
| 942 | nodeid = (limit & 0xf) + ((base>>4)&0x30); |
| 943 | } |
| 944 | reg_link = (limit >> 4) & 7; |
| 945 | reg_dev = __f0_dev[nodeid]; |
| 946 | if (reg_dev) { |
| 947 | /* Reserve the resource */ |
| 948 | struct resource *res; |
| 949 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 950 | if (res) { |
| 951 | res->flags = 1; |
| 952 | } |
| 953 | } |
| 954 | } |
| 955 | } |
| 956 | /* FIXME: do we need to check extend conf space? |
| 957 | I don't believe that much preset value */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 958 | pci_domain_read_resources(dev); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 959 | } |
| 960 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 961 | static void domain_enable_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 962 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 963 | } |
| 964 | |
| 965 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 966 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 967 | unsigned int hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 968 | int node_id; |
| 969 | }; |
| 970 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 971 | { |
| 972 | struct hw_mem_hole_info mem_hole; |
| 973 | int i; |
| 974 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 975 | mem_hole.node_id = -1; |
| 976 | for (i = 0; i < node_nums; i++) { |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame^] | 977 | resource_t basek, limitk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 978 | u32 hole; |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame^] | 979 | if (!get_dram_base_limit(i, &basek, &limitk)) |
| 980 | continue; // no memory on this node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 981 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 982 | if (hole & 2) { // we find the hole |
| 983 | mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; |
| 984 | mem_hole.node_id = i; // record the node No with hole |
| 985 | break; // only one hole |
| 986 | } |
| 987 | } |
| 988 | |
| 989 | /* We need to double check if there is special set on base reg and limit reg |
| 990 | * are not continuous instead of hole, it will find out its hole_startk. |
| 991 | */ |
| 992 | if (mem_hole.node_id == -1) { |
| 993 | resource_t limitk_pri = 0; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 994 | for (i = 0; i < node_nums; i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 995 | resource_t base_k, limit_k; |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame^] | 996 | if (!get_dram_base_limit(i, &base_k, &limit_k)) |
| 997 | continue; // no memory on this node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 998 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 999 | if (limitk_pri != base_k) { // we find the hole |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 1000 | mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1001 | mem_hole.node_id = i; |
| 1002 | break; //only one hole |
| 1003 | } |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1004 | limitk_pri = limit_k; |
| 1005 | } |
| 1006 | } |
| 1007 | return mem_hole; |
| 1008 | } |
| 1009 | #endif |
| 1010 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1011 | static void domain_set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1012 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1013 | unsigned long mmio_basek; |
| 1014 | u32 pci_tolm; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1015 | int i, idx; |
| 1016 | struct bus *link; |
| 1017 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 1018 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1019 | #endif |
| 1020 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1021 | pci_tolm = 0xffffffffUL; |
| 1022 | for (link = dev->link_list; link; link = link->next) { |
| 1023 | pci_tolm = find_pci_tolm(link); |
| 1024 | } |
| 1025 | |
| 1026 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 1027 | // amdk8, too. |
| 1028 | mmio_basek = pci_tolm >> 10; |
| 1029 | /* Round mmio_basek to something the processor can support */ |
| 1030 | mmio_basek &= ~((1 << 6) -1); |
| 1031 | |
| 1032 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 1033 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 1034 | /* Round the mmio hole to 64M */ |
| 1035 | mmio_basek &= ~((64*1024) - 1); |
| 1036 | |
| 1037 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 1038 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 1039 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 1040 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 1041 | * otherwise We reset the hole to the mmio_basek |
| 1042 | */ |
| 1043 | |
| 1044 | mem_hole = get_hw_mem_hole_info(); |
| 1045 | |
| 1046 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 1047 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 1048 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1049 | } |
| 1050 | #endif |
| 1051 | |
| 1052 | idx = 0x10; |
| 1053 | for (i = 0; i < node_nums; i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1054 | resource_t basek, limitk, sizek; // 4 1T |
| 1055 | |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame^] | 1056 | if (!get_dram_base_limit(i, &basek, &limitk)) |
| 1057 | continue; // no memory on this node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1058 | |
| 1059 | sizek = limitk - basek; |
| 1060 | |
| 1061 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
| 1062 | if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { |
| 1063 | ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); |
| 1064 | idx += 0x10; |
| 1065 | basek = (8*64)+(16*16); |
| 1066 | sizek = limitk - ((8*64)+(16*16)); |
| 1067 | |
| 1068 | } |
| 1069 | |
| 1070 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 1071 | |
| 1072 | /* split the region to accommodate pci memory space */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1073 | if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1074 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1075 | unsigned int pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1076 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1077 | if (pre_sizek > 0) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1078 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 1079 | idx += 0x10; |
| 1080 | sizek -= pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1081 | } |
| 1082 | basek = mmio_basek; |
| 1083 | } |
| 1084 | if ((basek + sizek) <= 4*1024*1024) { |
| 1085 | sizek = 0; |
| 1086 | } |
| 1087 | else { |
| 1088 | uint64_t topmem2 = bsp_topmem2(); |
| 1089 | basek = 4*1024*1024; |
| 1090 | sizek = topmem2/1024 - basek; |
| 1091 | } |
| 1092 | } |
| 1093 | |
| 1094 | ram_resource(dev, (idx | i), basek, sizek); |
| 1095 | idx += 0x10; |
| 1096 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 1097 | i, mmio_basek, basek, limitk); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1098 | } |
| 1099 | |
Kyösti Mälkki | e87564f | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 1100 | add_uma_resource_below_tolm(dev, 7); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1101 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 1102 | for (link = dev->link_list; link; link = link->next) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1103 | if (link->children) { |
| 1104 | assign_resources(link); |
| 1105 | } |
| 1106 | } |
| 1107 | } |
| 1108 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 1109 | static const char *domain_acpi_name(const struct device *dev) |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 1110 | { |
| 1111 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 1112 | return "PCI0"; |
| 1113 | |
| 1114 | return NULL; |
| 1115 | } |
| 1116 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1117 | static struct device_operations pci_domain_ops = { |
| 1118 | .read_resources = domain_read_resources, |
| 1119 | .set_resources = domain_set_resources, |
| 1120 | .enable_resources = domain_enable_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1121 | .scan_bus = pci_domain_scan_bus, |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 1122 | .acpi_name = domain_acpi_name, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1123 | }; |
| 1124 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1125 | static void sysconf_init(struct device *dev) // first node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1126 | { |
| 1127 | sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 |
| 1128 | node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 1129 | } |
| 1130 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1131 | static void cpu_bus_scan(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1132 | { |
| 1133 | struct bus *cpu_bus; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1134 | struct device *dev_mc; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1135 | int i,j; |
| 1136 | int coreid_bits; |
| 1137 | int core_max = 0; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1138 | unsigned int ApicIdCoreIdSize; |
| 1139 | unsigned int core_nums; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1140 | int siblings = 0; |
| 1141 | unsigned int family; |
| 1142 | u32 modules = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1143 | int ioapic_count = 0; |
| 1144 | |
Michał Żygowski | e719288 | 2019-11-23 19:02:19 +0100 | [diff] [blame] | 1145 | /* For binaryPI there is no multiprocessor configuration, the number of |
| 1146 | * modules will always be 1. */ |
| 1147 | modules = 1; |
| 1148 | ioapic_count = CONFIG_NUM_OF_IOAPICS; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1149 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1150 | dev_mc = pcidev_on_root(DEV_CDB, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1151 | if (!dev_mc) { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1152 | printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1153 | die(""); |
| 1154 | } |
| 1155 | sysconf_init(dev_mc); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1156 | |
| 1157 | /* Get Max Number of cores(MNC) */ |
Kyösti Mälkki | d41feed | 2017-09-24 16:23:57 +0300 | [diff] [blame] | 1158 | coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1159 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 1160 | |
| 1161 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); |
| 1162 | if (ApicIdCoreIdSize) { |
| 1163 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 1164 | } else { |
| 1165 | core_nums = 3; //quad core |
| 1166 | } |
| 1167 | |
| 1168 | /* Find which cpus are present */ |
| 1169 | cpu_bus = dev->link_list; |
| 1170 | for (i = 0; i < node_nums; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1171 | struct device *cdb_dev; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1172 | unsigned int devn; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1173 | struct bus *pbus; |
| 1174 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1175 | devn = DEV_CDB + i; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1176 | pbus = dev_mc->bus; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1177 | |
| 1178 | /* Find the cpu's pci device */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1179 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1180 | if (!cdb_dev) { |
| 1181 | /* If I am probing things in a weird order |
| 1182 | * ensure all of the cpu's pci devices are found. |
| 1183 | */ |
| 1184 | int fn; |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 1185 | for (fn = 0; fn <= 5; fn++) { //FBDIMM? |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1186 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 1187 | PCI_DEVFN(devn, fn)); |
| 1188 | } |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1189 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1190 | } else { |
| 1191 | /* Ok, We need to set the links for that device. |
| 1192 | * otherwise the device under it will not be scanned |
| 1193 | */ |
Kyösti Mälkki | c5163ed8 | 2015-02-04 13:25:37 +0200 | [diff] [blame] | 1194 | |
| 1195 | add_more_links(cdb_dev, 4); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1196 | } |
| 1197 | |
| 1198 | family = cpuid_eax(1); |
| 1199 | family = (family >> 20) & 0xFF; |
| 1200 | if (family == 1) { //f10 |
| 1201 | u32 dword; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1202 | cdb_dev = pcidev_on_root(devn, 3); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1203 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 1204 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 1205 | } else if (family == 7) {//f16 |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1206 | cdb_dev = pcidev_on_root(devn, 5); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1207 | if (cdb_dev && cdb_dev->enabled) { |
| 1208 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 1209 | siblings &= 0xFF; |
| 1210 | } |
| 1211 | } else { |
| 1212 | siblings = 0; //default one core |
| 1213 | } |
| 1214 | int enable_node = cdb_dev && cdb_dev->enabled; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1215 | printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1216 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 1217 | |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1218 | for (j = 0; j <= siblings; j++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1219 | u32 lapicid_start = 0; |
| 1220 | |
| 1221 | /* |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 1222 | * APIC ID calculation is tightly coupled with AGESA v5 code. |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1223 | * This calculation MUST match the assignment calculation done |
| 1224 | * in LocalApicInitializationAtEarly() function. |
| 1225 | * And reference GetLocalApicIdForCore() |
| 1226 | * |
Elyes HAOUAS | a5b0bc4 | 2020-02-20 20:04:29 +0100 | [diff] [blame] | 1227 | * Apply APIC enumeration rules |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1228 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 1229 | * put the local-APICs at m..z |
| 1230 | * |
| 1231 | * This is needed because many IO-APIC devices only have 4 bits |
| 1232 | * for their APIC id and therefore must reside at 0..15 |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 1233 | */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1234 | if ((node_nums * core_max) + ioapic_count >= 0x10) { |
| 1235 | lapicid_start = (ioapic_count - 1) / core_max; |
| 1236 | lapicid_start = (lapicid_start + 1) * core_max; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1237 | printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1238 | } |
| 1239 | u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1240 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1241 | i, j, apic_id); |
| 1242 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1243 | struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1244 | if (cpu) |
| 1245 | amd_cpu_topology(cpu, i, j); |
| 1246 | } //j |
| 1247 | } |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1248 | } |
| 1249 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1250 | static void cpu_bus_init(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1251 | { |
| 1252 | initialize_cpus(dev->link_list); |
| 1253 | } |
| 1254 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1255 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 1256 | .read_resources = noop_read_resources, |
| 1257 | .set_resources = noop_set_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1258 | .init = cpu_bus_init, |
| 1259 | .scan_bus = cpu_bus_scan, |
| 1260 | }; |
| 1261 | |
| 1262 | static void root_complex_enable_dev(struct device *dev) |
| 1263 | { |
| 1264 | static int done = 0; |
| 1265 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1266 | if (!done) { |
| 1267 | setup_bsp_ramtop(); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1268 | done = 1; |
| 1269 | } |
| 1270 | |
| 1271 | /* Set the operations if it is a special bus type */ |
| 1272 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 1273 | dev->ops = &pci_domain_ops; |
| 1274 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 1275 | dev->ops = &cpu_bus_ops; |
| 1276 | } |
| 1277 | } |
| 1278 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1279 | struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1280 | CHIP_NAME("AMD FAM16 Root Complex") |
| 1281 | .enable_dev = root_complex_enable_dev, |
| 1282 | }; |
| 1283 | |
| 1284 | /********************************************************************* |
| 1285 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 1286 | *********************************************************************/ |
| 1287 | u32 map_oprom_vendev(u32 vendev) |
| 1288 | { |
| 1289 | u32 new_vendev; |
| 1290 | new_vendev = |
| 1291 | ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; |
| 1292 | |
| 1293 | if (vendev != new_vendev) |
| 1294 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 1295 | |
| 1296 | return new_vendev; |
| 1297 | } |