cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index f4c39d6..7125e1e 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -28,11 +28,15 @@
#include <lib.h>
#include <cpu/cpu.h>
#include <cbmem.h>
-
#include <Porting.h>
#include <AGESA.h>
#include <FieldAccessors.h>
#include <Topology.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
@@ -40,11 +44,6 @@
#endif
#include "northbridge.h"
-#include <cpu/x86/lapic.h>
-#include <cpu/amd/mtrr.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-
#define MAX_NODE_NUMS MAX_NODES
typedef struct dram_base_mask {
@@ -312,7 +311,7 @@
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
- mmconf_resource(dev, 0xc0010058);
+ mmconf_resource(dev, MMIO_CONF_BASE);
}
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)