cpu/amd/pi/00730F01: Use common code for mp_init
TEST=APU2 still boots and doesn't show any new errors in dmesg.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index f1a69c2..55a0dab 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -849,21 +849,11 @@
.acpi_name = domain_acpi_name,
};
-static void pre_mp_init(void)
-{
- x86_setup_mtrrs_with_detect();
- x86_mtrr_check();
-}
-
-static const struct mp_ops mp_ops = {
- .pre_mp_init = pre_mp_init,
- .get_cpu_count = get_cpu_count,
-};
-
void mp_init_cpus(struct bus *cpu_bus)
{
+ extern const struct mp_ops amd_mp_ops_no_smm;
/* TODO: Handle mp_init_with_smm failure? */
- mp_init_with_smm(cpu_bus, &mp_ops);
+ mp_init_with_smm(cpu_bus, &amd_mp_ops_no_smm);
/* The flash is now no longer cacheable. Reset to WP for performance. */
mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,