Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Frans Hendriks | ad5e0a8 | 2019-03-18 13:31:56 +0100 | [diff] [blame] | 6 | #include <arch/ioapic.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 7 | #include <bootstate.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 8 | #include "chip.h" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 9 | #include <console/console.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 13 | #include <intelblocks/lpc_lib.h> |
Frans Hendriks | 255f35c | 2018-12-11 15:21:47 +0100 | [diff] [blame] | 14 | #include <pc80/isa-dma.h> |
Frans Hendriks | bd5233e | 2018-12-05 15:24:48 +0100 | [diff] [blame] | 15 | #include <pc80/i8254.h> |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 16 | #include <pc80/i8259.h> |
Lee Leahy | 2bc9cee | 2015-06-30 15:25:44 -0700 | [diff] [blame] | 17 | #include <soc/acpi.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | #include <soc/iomap.h> |
| 19 | #include <soc/irq.h> |
| 20 | #include <soc/lpc.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 22 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 23 | #include <soc/ramstage.h> |
| 24 | #include <soc/spi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 25 | #include <spi-generic.h> |
| 26 | #include <stdint.h> |
Arthur Heymans | 68b6eb7 | 2019-10-13 23:26:36 +0200 | [diff] [blame] | 27 | #include <southbridge/intel/common/spi.h> |
Hannah Williams | 3fa80a9 | 2017-03-22 16:33:36 -0700 | [diff] [blame] | 28 | |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 29 | static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode) |
Hannah Williams | 3fa80a9 | 2017-03-22 16:33:36 -0700 | [diff] [blame] | 30 | { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 31 | u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xf); |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 32 | |
| 33 | switch (mode) { |
| 34 | case SERIRQ_CONTINUOUS: |
| 35 | break; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 36 | |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 37 | case SERIRQ_OFF: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 38 | write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) & ~SIRQEN); |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 39 | break; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 40 | |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 41 | case SERIRQ_QUIET: |
| 42 | default: |
| 43 | write8(ilb_base + SCNT, read8(ilb_base + SCNT) & ~SCNT_MODE); |
| 44 | break; |
| 45 | } |
Hannah Williams | 3fa80a9 | 2017-03-22 16:33:36 -0700 | [diff] [blame] | 46 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 47 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 48 | static void sc_add_mmio_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 49 | { |
Kyösti Mälkki | 5a55a45 | 2021-06-24 20:49:05 +0300 | [diff] [blame] | 50 | mmio_range(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 51 | mmio_range(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 52 | mmio_range(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 53 | mmio_range(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 54 | mmio_range(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 55 | mmio_range(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 56 | mmio_range(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 57 | mmio_range(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
| 58 | mmio_range(dev, 0xfff, 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB * KiB) + 1, |
| 59 | CONFIG_COREBOOT_ROMSIZE_KB * KiB); /* BIOS ROM */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 60 | |
Kyösti Mälkki | 5a55a45 | 2021-06-24 20:49:05 +0300 | [diff] [blame] | 61 | mmio_range(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 65 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 66 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 67 | |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 68 | static void sc_enable_serial_irqs(struct device *dev) |
| 69 | { |
| 70 | u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); |
| 71 | |
| 72 | printk(BIOS_SPEW, "Enable serial irq\n"); |
| 73 | write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) | SIRQEN); |
| 74 | write8(ilb_base + SCNT, read8(ilb_base + SCNT) | SCNT_MODE); |
| 75 | } |
| 76 | |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 77 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 78 | * Write PCI config space IRQ assignments. PCI devices have the INT_LINE (0x3c) and INT_PIN |
| 79 | * (0x3d) registers which report interrupt routing information to operating systems and drivers. |
| 80 | * The INT_PIN register is generally read only and reports which interrupt pin A - D it uses. |
| 81 | * The INT_LINE register is configurable and reports which IRQ (generally the PIC IRQs 1 - 15) |
| 82 | * it will use. This needs to take interrupt pin swizzling on devices that are downstream on |
| 83 | * a PCI bridge into account. |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 84 | * |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 85 | * This function will loop through all enabled PCI devices and program the INT_LINE register |
| 86 | * with the correct PIC IRQ number for the INT_PIN that it uses. It then configures each |
| 87 | * interrupt in the PIC to be level triggered. |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 88 | */ |
| 89 | static void write_pci_config_irqs(void) |
| 90 | { |
| 91 | struct device *irq_dev; |
| 92 | struct device *targ_dev; |
| 93 | uint8_t int_line = 0; |
| 94 | uint8_t original_int_pin = 0; |
| 95 | uint8_t new_int_pin = 0; |
| 96 | uint16_t current_bdf = 0; |
| 97 | uint16_t parent_bdf = 0; |
| 98 | uint8_t pirq = 0; |
| 99 | uint8_t device_num = 0; |
| 100 | const struct soc_irq_route *ir = &global_soc_irq_route; |
| 101 | |
| 102 | if (ir == NULL) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 103 | printk(BIOS_WARNING, "Can't write PCI IRQ assignments " |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 104 | "because 'global_braswell_irq_route' structure does not exist\n"); |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 105 | return; |
| 106 | } |
| 107 | |
| 108 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 109 | * Loop through all enabled devices and program their INT_LINE, INT_PIN registers from |
| 110 | * values taken from the Interrupt Route registers in the ILB |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 111 | */ |
| 112 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PIRQ assignments\n"); |
| 113 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 114 | |
| 115 | if ((irq_dev->path.type != DEVICE_PATH_PCI) || |
| 116 | (!irq_dev->enabled)) |
| 117 | continue; |
| 118 | |
| 119 | current_bdf = irq_dev->path.pci.devfn | |
| 120 | irq_dev->bus->secondary << 8; |
| 121 | |
| 122 | /* |
| 123 | * Step 1: Get the INT_PIN and device structure to look for |
| 124 | * in the pirq_data table defined in the mainboard directory. |
| 125 | */ |
| 126 | targ_dev = NULL; |
| 127 | new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); |
| 128 | if (targ_dev == NULL || new_int_pin < 1) |
| 129 | continue; |
| 130 | |
| 131 | /* Get the original INT_PIN for record keeping */ |
| 132 | original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 133 | |
| 134 | parent_bdf = targ_dev->path.pci.devfn |
| 135 | | targ_dev->bus->secondary << 8; |
| 136 | device_num = PCI_SLOT(parent_bdf); |
| 137 | |
| 138 | if (ir->pcidev[device_num] == 0) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 139 | printk(BIOS_WARNING, "PCI Device %d does not have an IRQ entry, " |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 140 | "skipping it\n", device_num); |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 141 | continue; |
| 142 | } |
| 143 | |
| 144 | /* Find the PIRQ that is attached to the INT_PIN */ |
| 145 | pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) |
| 146 | & 0x7; |
| 147 | |
| 148 | /* Get the INT_LINE this device/function will use */ |
| 149 | int_line = ir->pic[pirq]; |
| 150 | |
| 151 | if (int_line != PIRQ_PIC_IRQDISABLE) { |
| 152 | /* Set this IRQ to level triggered */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 153 | i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); |
| 154 | |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 155 | /* Set the Interrupt Line register */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 156 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 157 | } else { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 158 | /* Set the Interrupt line register as 'unknown' or 'unused' */ |
| 159 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, PIRQ_PIC_UNKNOWN_UNUSED); |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 160 | } |
| 161 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 162 | printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", original_int_pin, |
| 163 | pin_to_str(original_int_pin)); |
| 164 | |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 165 | if (parent_bdf != current_bdf) |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 166 | printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", new_int_pin, |
| 167 | pin_to_str(new_int_pin)); |
| 168 | |
| 169 | printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n\tINT_LINE\t: 0x%X (IRQ %d)\n", |
| 170 | 'A' + pirq, int_line, int_line); |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 171 | } |
| 172 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PIRQ assignments\n"); |
| 173 | } |
| 174 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 175 | static inline int io_range_in_default(int base, int size) |
| 176 | { |
| 177 | /* Does it start above the range? */ |
| 178 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 179 | return 0; |
| 180 | |
| 181 | /* Is it entirely contained? */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 182 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 183 | return 1; |
| 184 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 185 | /* This will return not in range for partial overlaps */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | /* |
| 190 | * Note: this function assumes there is no overlap with the default LPC device's |
| 191 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 192 | */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 193 | static void sc_add_io_resource(struct device *dev, int base, int size, int index) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 194 | { |
| 195 | struct resource *res; |
| 196 | |
| 197 | if (io_range_in_default(base, size)) |
| 198 | return; |
| 199 | |
| 200 | res = new_resource(dev, index); |
| 201 | res->base = base; |
| 202 | res->size = size; |
| 203 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 204 | } |
| 205 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 206 | static void sc_add_io_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 207 | { |
| 208 | struct resource *res; |
| 209 | |
| 210 | /* Add the default claimed IO range for the LPC device. */ |
| 211 | res = new_resource(dev, 0); |
| 212 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 213 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 214 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 215 | |
| 216 | /* GPIO */ |
Frans Hendriks | 4b2c12f | 2018-11-22 07:52:38 +0100 | [diff] [blame] | 217 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 218 | |
| 219 | /* ACPI */ |
Frans Hendriks | 4b2c12f | 2018-11-22 07:52:38 +0100 | [diff] [blame] | 220 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 221 | } |
| 222 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 223 | static void sc_read_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 224 | { |
| 225 | /* Get the normal PCI resources of this device. */ |
| 226 | pci_dev_read_resources(dev); |
| 227 | |
| 228 | /* Add non-standard MMIO resources. */ |
| 229 | sc_add_mmio_resources(dev); |
| 230 | |
| 231 | /* Add IO resources. */ |
| 232 | sc_add_io_resources(dev); |
| 233 | } |
| 234 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 235 | static void sc_init(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 236 | { |
| 237 | int i; |
Frans Hendriks | b55cd54 | 2019-03-06 14:45:12 +0100 | [diff] [blame] | 238 | const unsigned long ilb_base = ILB_BASE_ADDRESS; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 239 | const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; |
| 240 | const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; |
| 241 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 242 | void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 243 | const struct soc_irq_route *ir = &global_soc_irq_route; |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 244 | struct soc_intel_braswell_config *config = config_of(dev); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 245 | |
Frans Hendriks | b55cd54 | 2019-03-06 14:45:12 +0100 | [diff] [blame] | 246 | /* Set the value for PCI command register. */ |
| 247 | pci_write_config16(dev, PCI_COMMAND, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 248 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
Frans Hendriks | b55cd54 | 2019-03-06 14:45:12 +0100 | [diff] [blame] | 249 | |
| 250 | /* Use IRQ9 for SCI Interrupt */ |
| 251 | write32((void *)(ilb_base + ACTL), 0); |
| 252 | |
Frans Hendriks | 255f35c | 2018-12-11 15:21:47 +0100 | [diff] [blame] | 253 | isa_dma_init(); |
| 254 | |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 255 | sc_enable_serial_irqs(dev); |
| 256 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 257 | /* Set up the PIRQ PIC routing based on static config. */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 258 | for (i = 0; i < NUM_PIRQS; i++) |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 259 | write8((void *)(pr_base + i*sizeof(ir->pic[i])), ir->pic[i]); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 260 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 261 | /* Set up the per device PIRQ routing base on static config. */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 262 | for (i = 0; i < NUM_IR_DEVS; i++) |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 263 | write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 264 | |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 265 | /* Interrupt 9 should be level triggered (SCI) */ |
| 266 | i8259_configure_irq_trigger(9, 1); |
| 267 | |
| 268 | for (i = 0; i < NUM_PIRQS; i++) { |
| 269 | if (ir->pic[i]) |
| 270 | i8259_configure_irq_trigger(ir->pic[i], 1); |
| 271 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 272 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 273 | if (config->disable_slp_x_stretch_sus_fail) { |
| 274 | printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 275 | write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); |
| 276 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 277 | } else { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 278 | write32(gen_pmcon1, read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 279 | } |
| 280 | |
Frans Hendriks | 9348413 | 2018-12-10 12:38:16 +0100 | [diff] [blame] | 281 | /* Write IRQ assignments to PCI config space */ |
| 282 | write_pci_config_irqs(); |
| 283 | |
| 284 | /* Initialize i8259 pic */ |
| 285 | setup_i8259(); |
| 286 | |
Frans Hendriks | bd5233e | 2018-12-05 15:24:48 +0100 | [diff] [blame] | 287 | /* Initialize i8254 timers */ |
| 288 | setup_i8254(); |
Frans Hendriks | 2c63017 | 2019-04-02 15:06:29 +0200 | [diff] [blame] | 289 | |
| 290 | sc_set_serial_irqs_mode(dev, config->serirq_mode); |
| 291 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 292 | } |
| 293 | |
| 294 | /* |
| 295 | * Common code for the south cluster devices. |
| 296 | */ |
| 297 | |
Frans Hendriks | e6bf51f | 2019-05-01 10:48:31 +0200 | [diff] [blame] | 298 | /* Set bit in function disable register to hide this device. */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 299 | static void sc_disable_devfn(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 300 | { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 301 | void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 302 | void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 303 | uint32_t mask = 0; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 304 | uint32_t mask2 = 0; |
| 305 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 306 | #define SET_DIS_MASK(name_) \ |
| 307 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 308 | mask |= name_ ## _DIS |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 309 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 310 | #define SET_DIS_MASK2(name_) \ |
| 311 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 312 | mask2 |= name_ ## _DIS |
| 313 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 314 | switch (dev->path.pci.devfn) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 315 | SET_DIS_MASK(SDIO); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 316 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 317 | SET_DIS_MASK(SD); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 318 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 319 | SET_DIS_MASK(SATA); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 320 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 321 | SET_DIS_MASK(XHCI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 322 | /* Disable super speed PHY when XHCI is not available. */ |
| 323 | mask2 |= USH_SS_PHY_DIS; |
| 324 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 325 | SET_DIS_MASK(LPE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 326 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 327 | SET_DIS_MASK(MMC); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 328 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 329 | SET_DIS_MASK(SIO_DMA1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 330 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 331 | SET_DIS_MASK(I2C1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 332 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 333 | SET_DIS_MASK(I2C2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 334 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 335 | SET_DIS_MASK(I2C3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 336 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 337 | SET_DIS_MASK(I2C4); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 338 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 339 | SET_DIS_MASK(I2C5); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 340 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 341 | SET_DIS_MASK(I2C6); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 342 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 343 | SET_DIS_MASK(I2C7); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 344 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 345 | SET_DIS_MASK(TXE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 346 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 347 | SET_DIS_MASK(HDA); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 348 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 349 | SET_DIS_MASK(PCIE_PORT1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 350 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 351 | SET_DIS_MASK(PCIE_PORT2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 352 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 353 | SET_DIS_MASK(PCIE_PORT3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 354 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 355 | SET_DIS_MASK(PCIE_PORT4); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 356 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 357 | SET_DIS_MASK(SIO_DMA2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 358 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 359 | SET_DIS_MASK(PWM1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 360 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 361 | SET_DIS_MASK(PWM2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 362 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 363 | SET_DIS_MASK(HSUART1); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 364 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 365 | SET_DIS_MASK(HSUART2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 366 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 367 | SET_DIS_MASK(SPI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 368 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 369 | SET_DIS_MASK2(SMBUS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 370 | break; |
| 371 | } |
| 372 | |
| 373 | if (mask != 0) { |
| 374 | write32(func_dis, read32(func_dis) | mask); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 375 | /* Ensure posted write hits */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 376 | read32(func_dis); |
| 377 | } |
| 378 | |
| 379 | if (mask2 != 0) { |
| 380 | write32(func_dis2, read32(func_dis2) | mask2); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 381 | /* Ensure posted write hits */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 382 | read32(func_dis2); |
| 383 | } |
| 384 | } |
| 385 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 386 | static inline void set_d3hot_bits(struct device *dev, int offset) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 387 | { |
| 388 | uint32_t reg8; |
| 389 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 390 | reg8 = pci_read_config8(dev, offset + 4); |
| 391 | reg8 |= 0x3; |
| 392 | pci_write_config8(dev, offset + 4, reg8); |
| 393 | } |
| 394 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 395 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 396 | * Parts of the audio subsystem are powered by the HDA device. Thus, one cannot put HDA into |
| 397 | * D3Hot. Instead, perform this workaround to make some of the audio paths work for LPE audio. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 398 | */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 399 | static void hda_work_around(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 400 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 401 | void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); |
| 402 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 403 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 404 | pci_write_config8(dev, 0x43, 0xd7); |
| 405 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 406 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 407 | * Need to set bit 0 of GCTL to take the device out of reset. |
| 408 | * However, that requires setting up the 64-bit BAR. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 409 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 410 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 411 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 412 | pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 413 | write32(gctl, read32(gctl) | 0x1); |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 414 | pci_write_config16(dev, PCI_COMMAND, 0); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 415 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 416 | } |
| 417 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 418 | static int place_device_in_d3hot(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 419 | { |
Lee Leahy | 1072e7d | 2017-03-16 17:35:32 -0700 | [diff] [blame] | 420 | unsigned int offset; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 421 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 422 | /* |
| 423 | * Parts of the HDA block are used for LPE audio as well. |
| 424 | * Therefore assume the HDA will never be put into D3Hot. |
| 425 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 426 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 427 | hda_work_around(dev); |
| 428 | return 0; |
| 429 | } |
| 430 | |
| 431 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 432 | |
| 433 | if (offset != 0) { |
| 434 | set_d3hot_bits(dev, offset); |
| 435 | return 0; |
| 436 | } |
| 437 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 438 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 439 | * For some reason some of the devices don't have the capability pointer set correctly. |
| 440 | * Work around this by hard coding the offset. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 441 | */ |
| 442 | #define DEV_CASE(name_) \ |
| 443 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) |
| 444 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 445 | switch (dev->path.pci.devfn) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 446 | DEV_CASE(SDIO) : |
| 447 | DEV_CASE(SD) : |
| 448 | DEV_CASE(MMC) : |
| 449 | DEV_CASE(LPE) : |
| 450 | DEV_CASE(SIO_DMA1) : |
| 451 | DEV_CASE(I2C1) : |
| 452 | DEV_CASE(I2C2) : |
| 453 | DEV_CASE(I2C3) : |
| 454 | DEV_CASE(I2C4) : |
| 455 | DEV_CASE(I2C5) : |
| 456 | DEV_CASE(I2C6) : |
| 457 | DEV_CASE(I2C7) : |
| 458 | DEV_CASE(SIO_DMA2) : |
| 459 | DEV_CASE(PWM1) : |
| 460 | DEV_CASE(PWM2) : |
| 461 | DEV_CASE(HSUART1) : |
| 462 | DEV_CASE(HSUART2) : |
| 463 | DEV_CASE(SPI) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 464 | offset = 0x80; |
| 465 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 466 | DEV_CASE(SATA) : |
| 467 | DEV_CASE(XHCI) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 468 | offset = 0x70; |
| 469 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 470 | DEV_CASE(HDA) : |
| 471 | DEV_CASE(SMBUS) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 472 | offset = 0x50; |
| 473 | break; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 474 | DEV_CASE(TXE) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 475 | /* TXE cannot be placed in D3Hot. */ |
| 476 | return 0; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 477 | DEV_CASE(PCIE_PORT1) : |
| 478 | DEV_CASE(PCIE_PORT2) : |
| 479 | DEV_CASE(PCIE_PORT3) : |
| 480 | DEV_CASE(PCIE_PORT4) : |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 481 | offset = 0xa0; |
| 482 | break; |
| 483 | } |
| 484 | |
| 485 | if (offset != 0) { |
| 486 | set_d3hot_bits(dev, offset); |
| 487 | return 0; |
| 488 | } |
| 489 | |
| 490 | return -1; |
| 491 | } |
| 492 | |
| 493 | /* Common PCI device function disable. */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 494 | void southcluster_enable_dev(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 495 | { |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 496 | uint16_t reg16; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 497 | |
| 498 | if (!dev->enabled) { |
| 499 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 500 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 501 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 502 | dev_path(dev), slot, func); |
| 503 | |
| 504 | /* Ensure memory, io, and bus master are all disabled */ |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 505 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 506 | reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 507 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 508 | |
| 509 | /* Place device in D3Hot */ |
| 510 | if (place_device_in_d3hot(dev) < 0) { |
| 511 | printk(BIOS_WARNING, |
| 512 | "Could not place %02x.%01x into D3Hot. " |
| 513 | "Keeping device visible.\n", slot, func); |
| 514 | return; |
| 515 | } |
| 516 | /* Disable this device if possible */ |
| 517 | sc_disable_devfn(dev); |
| 518 | } else { |
| 519 | /* Enable SERR */ |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 520 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 521 | } |
| 522 | } |
| 523 | |
| 524 | static struct device_operations device_ops = { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 525 | .read_resources = sc_read_resources, |
| 526 | .set_resources = pci_dev_set_resources, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 527 | .write_acpi_tables = southcluster_write_acpi_tables, |
| 528 | .init = sc_init, |
| 529 | .enable = southcluster_enable_dev, |
| 530 | .scan_bus = scan_static_bus, |
| 531 | .ops_pci = &soc_pci_ops, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 532 | }; |
| 533 | |
| 534 | static const struct pci_driver southcluster __pci_driver = { |
| 535 | .ops = &device_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 536 | .vendor = PCI_VID_INTEL, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 537 | .device = LPC_DEVID, |
| 538 | }; |
| 539 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 540 | static void finalize_chipset(void *unused) |
| 541 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 542 | void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); |
| 543 | void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); |
| 544 | void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); |
| 545 | void *etr = (void *)(PMC_BASE_ADDRESS + ETR); |
| 546 | uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 547 | |
Arthur Heymans | 68b6eb7 | 2019-10-13 23:26:36 +0200 | [diff] [blame] | 548 | struct vscc_config cfg; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 549 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 550 | /* Set the lock enable on the BIOS control register */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 551 | write32(bcr, read32(bcr) | BCR_LE); |
| 552 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 553 | /* Set BIOS lock down bit controlling boot block size and swapping */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 554 | write32(gcs, read32(gcs) | BILD); |
| 555 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 556 | /* Lock sleep stretching policy and set SMI lock */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 557 | write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); |
| 558 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 559 | /* Set the CF9 lock */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 560 | write32(etr, read32(etr) | CF9LOCK); |
| 561 | |
Arthur Heymans | 68b6eb7 | 2019-10-13 23:26:36 +0200 | [diff] [blame] | 562 | spi_finalize_ops(); |
| 563 | write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); |
| 564 | |
| 565 | if (mainboard_get_spi_vscc_config(&cfg) < 0) { |
| 566 | printk(BIOS_DEBUG, "No SPI VSCC configuration.\n"); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 567 | } else { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 568 | write32(spi + UVSCC, cfg.uvscc); |
| 569 | write32(spi + LVSCC, cfg.lvscc | VCL); |
| 570 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 571 | } |
| 572 | |
Hannah Williams | 2cfdde7 | 2015-04-15 19:48:07 -0700 | [diff] [blame] | 573 | BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, finalize_chipset, NULL); |