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review.coreboot.org / coreboot / 6e53ae6f5c12b70c2a86370f0dd9df37a12c8118 / . / src / soc / intel / skylake / acpi / scs.asl
blob: aea44834737e39deff63aca2303cb552a0506cb5 [file] [log] [blame]
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Google Inc.
5 * Copyright (C) 2015 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]15 */
16
17/* Intel Storage Controllers */
18
19Device (EMMC)
20{
21 Name (_ADR, 0x001E0004)
22 Name (_DDN, "eMMC Controller")
23
24 OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
25 Field (EMCR, DWordAcc, NoLock, Preserve)
26 {
27 Offset (0x84), /* PMECTRLSTATUS */
28 D0D3, 2, /* POWERSTATE */
29 Offset (0xa2), /* PG_CONFIG */
30 , 2,
31 PGEN, 1, /* PG_ENABLE */
32 }
33
34 Method (_PS0, 0, Serialized)
35 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]36 /* Disable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]37 Store (0, ^PGEN)
38
39 /* Clear bits 31, 6, 2, 0 */
40 ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA)
41 Sleep (2)
42
43 /* Set bits 31, 6, 2, 0 */
44 ^^PCRO (PID_SCS, 0x600, 0x80000045)
45
46 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]47 Store (Zero, Local0)
48 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]49 Store (^D0D3, Local0)
50 }
51
52 Method (_PS3, 0, Serialized)
53 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]54 /* Enable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]55 Store (1, ^PGEN)
56
57 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]58 Store (3, Local0)
59 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]60 Store (^D0D3, Local0)
61 }
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]62}
63
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame]64#if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]65Device (SDXC)
66{
67 Name (_ADR, 0x001E0006)
68 Name (_DDN, "SD Controller")
69
70 OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
71 Field (SDCR, DWordAcc, NoLock, Preserve)
72 {
73 Offset (0x84), /* PMECTRLSTATUS */
74 D0D3, 2, /* POWERSTATE */
75 Offset (0xa2), /* PG_CONFIG */
76 , 2,
77 PGEN, 1, /* PG_ENABLE */
78 }
79
80 Method (_PS0, 0, Serialized)
81 {
Zhuo-hao.Leece37e472016-07-27 13:18:22 +0800[diff] [blame]82 /* Disable 20K pull-down on CLK, CMD and DAT lines */
83 ^^PCRA (PID_GPIOCOM3, 0x4c4, 0xFFFFEFFF)
84 ^^PCRA (PID_GPIOCOM3, 0x4cc, 0xFFFFEFFF)
85 ^^PCRA (PID_GPIOCOM3, 0x4d4, 0xFFFFEFFF)
86 ^^PCRA (PID_GPIOCOM3, 0x4dc, 0xFFFFEFFF)
87 ^^PCRA (PID_GPIOCOM3, 0x4e4, 0xFFFFEFFF)
88 ^^PCRA (PID_GPIOCOM3, 0x4f4, 0xFFFFEFFF)
89
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]90 /* Disable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]91 Store (0, ^PGEN)
92
93 /* Clear bits 8, 7, 2, 0 */
94 ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
95 Sleep (2)
96
97 /* Set bits 31, 6, 2, 0 */
98 ^^PCRO (PID_SCS, 0x600, 0x00000185)
99
100 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]101 Store (Zero, Local0)
102 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]103 Store (^D0D3, Local0)
104 }
105
106 Method (_PS3, 0, Serialized)
107 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]108 /* Enable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]109 Store (1, ^PGEN)
110
111 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]112 Store (3, Local0)
113 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]114 Store (^D0D3, Local0)
Zhuo-hao.Leece37e472016-07-27 13:18:22 +0800[diff] [blame]115
116 /* Enable 20K pull-down on CLK, CMD and DAT lines */
117 ^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000)
118 ^^PCRO (PID_GPIOCOM3, 0x4cc, 0x00001000)
119 ^^PCRO (PID_GPIOCOM3, 0x4d4, 0x00001000)
120 ^^PCRO (PID_GPIOCOM3, 0x4dc, 0x00001000)
121 ^^PCRO (PID_GPIOCOM3, 0x4e4, 0x00001000)
122 ^^PCRO (PID_GPIOCOM3, 0x4f4, 0x00001000)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]123 }
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]124}
Martin Rothbb9722b2016-07-28 16:32:56 -0600[diff] [blame]125#endif