Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 086730b0629237c9f171515b82b617ef27f73492 / . / src / soc / intel / skylake / acpi / scs.asl
blob: 56f27a97ea2a417d729c9fe4b962dcf8153414c7 [file] [log] [blame]
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Google Inc.
5 * Copyright (C) 2015 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]15 */
16
17/* Intel Storage Controllers */
18
19Device (EMMC)
20{
21 Name (_ADR, 0x001E0004)
22 Name (_DDN, "eMMC Controller")
23
24 OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
25 Field (EMCR, DWordAcc, NoLock, Preserve)
26 {
27 Offset (0x84), /* PMECTRLSTATUS */
28 D0D3, 2, /* POWERSTATE */
29 Offset (0xa2), /* PG_CONFIG */
30 , 2,
31 PGEN, 1, /* PG_ENABLE */
32 }
33
34 Method (_PS0, 0, Serialized)
35 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]36 /* Disable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]37 Store (0, ^PGEN)
38
39 /* Clear bits 31, 6, 2, 0 */
40 ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA)
41 Sleep (2)
42
43 /* Set bits 31, 6, 2, 0 */
44 ^^PCRO (PID_SCS, 0x600, 0x80000045)
45
46 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]47 Store (Zero, Local0)
48 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]49 Store (^D0D3, Local0)
50 }
51
52 Method (_PS3, 0, Serialized)
53 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]54 /* Enable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]55 Store (1, ^PGEN)
56
57 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]58 Store (3, Local0)
59 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]60 Store (^D0D3, Local0)
61 }
62
63 Device (CARD)
64 {
65 Name (_ADR, 0x00000008)
66 Method (_RMV, 0, NotSerialized)
67 {
68 Return (0)
69 }
70 }
71}
72
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame^]73#if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]74Device (SDXC)
75{
76 Name (_ADR, 0x001E0006)
77 Name (_DDN, "SD Controller")
78
79 OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
80 Field (SDCR, DWordAcc, NoLock, Preserve)
81 {
82 Offset (0x84), /* PMECTRLSTATUS */
83 D0D3, 2, /* POWERSTATE */
84 Offset (0xa2), /* PG_CONFIG */
85 , 2,
86 PGEN, 1, /* PG_ENABLE */
87 }
88
89 Method (_PS0, 0, Serialized)
90 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]91 /* Disable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]92 Store (0, ^PGEN)
93
94 /* Clear bits 8, 7, 2, 0 */
95 ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
96 Sleep (2)
97
98 /* Set bits 31, 6, 2, 0 */
99 ^^PCRO (PID_SCS, 0x600, 0x00000185)
100
101 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]102 Store (Zero, Local0)
103 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]104 Store (^D0D3, Local0)
105 }
106
107 Method (_PS3, 0, Serialized)
108 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]109 /* Enable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]110 Store (1, ^PGEN)
111
112 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame]113 Store (3, Local0)
114 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]115 Store (^D0D3, Local0)
116 }
117
118 Device (CARD)
119 {
120 Name (_ADR, 0x00000008)
121 Method (_RMV, 0, NotSerialized)
122 {
123 Return (1)
124 }
125 }
126}
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame^]127#endif