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review.coreboot.org / coreboot / aa1b6b06ef506eeb4cc73139b473a0aeb9ee26ba / . / src / soc / intel / skylake / acpi / scs.asl
blob: 0a6d94b0b872de6ed06af0142a3ea2df9bccd153 [file] [log] [blame]
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Google Inc.
5 * Copyright (C) 2015 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.
19 */
20
21/* Intel Storage Controllers */
22
23Device (EMMC)
24{
25 Name (_ADR, 0x001E0004)
26 Name (_DDN, "eMMC Controller")
27
28 OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
29 Field (EMCR, DWordAcc, NoLock, Preserve)
30 {
31 Offset (0x84), /* PMECTRLSTATUS */
32 D0D3, 2, /* POWERSTATE */
33 Offset (0xa2), /* PG_CONFIG */
34 , 2,
35 PGEN, 1, /* PG_ENABLE */
36 }
37
38 Method (_PS0, 0, Serialized)
39 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame^]40 /* Disable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]41 Store (0, ^PGEN)
42
43 /* Clear bits 31, 6, 2, 0 */
44 ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA)
45 Sleep (2)
46
47 /* Set bits 31, 6, 2, 0 */
48 ^^PCRO (PID_SCS, 0x600, 0x80000045)
49
50 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame^]51 Store (Zero, Local0)
52 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]53 Store (^D0D3, Local0)
54 }
55
56 Method (_PS3, 0, Serialized)
57 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame^]58 /* Enable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]59 Store (1, ^PGEN)
60
61 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame^]62 Store (3, Local0)
63 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]64 Store (^D0D3, Local0)
65 }
66
67 Device (CARD)
68 {
69 Name (_ADR, 0x00000008)
70 Method (_RMV, 0, NotSerialized)
71 {
72 Return (0)
73 }
74 }
75}
76
77Device (SDXC)
78{
79 Name (_ADR, 0x001E0006)
80 Name (_DDN, "SD Controller")
81
82 OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
83 Field (SDCR, DWordAcc, NoLock, Preserve)
84 {
85 Offset (0x84), /* PMECTRLSTATUS */
86 D0D3, 2, /* POWERSTATE */
87 Offset (0xa2), /* PG_CONFIG */
88 , 2,
89 PGEN, 1, /* PG_ENABLE */
90 }
91
92 Method (_PS0, 0, Serialized)
93 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame^]94 /* Disable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]95 Store (0, ^PGEN)
96
97 /* Clear bits 8, 7, 2, 0 */
98 ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
99 Sleep (2)
100
101 /* Set bits 31, 6, 2, 0 */
102 ^^PCRO (PID_SCS, 0x600, 0x00000185)
103
104 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame^]105 Store (Zero, Local0)
106 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]107 Store (^D0D3, Local0)
108 }
109
110 Method (_PS3, 0, Serialized)
111 {
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame^]112 /* Enable Power Gate */
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]113 Store (1, ^PGEN)
114
115 /* Set Power State to D0 */
Duncan Laurieaa1b6b02015-09-23 18:01:45 -0700[diff] [blame^]116 Store (3, Local0)
117 Store (Local0, ^D0D3)
Duncan Laurie86f23ac2015-08-27 16:53:45 -0700[diff] [blame]118 Store (^D0D3, Local0)
119 }
120
121 Device (CARD)
122 {
123 Name (_ADR, 0x00000008)
124 Method (_RMV, 0, NotSerialized)
125 {
126 Return (1)
127 }
128 }
129}