| Duncan Laurie | 86f23ac | 2015-08-27 16:53:45 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | /* Intel Storage Controllers */ |
| 22 | |
| 23 | Device (EMMC) |
| 24 | { |
| 25 | Name (_ADR, 0x001E0004) |
| 26 | Name (_DDN, "eMMC Controller") |
| 27 | |
| 28 | OperationRegion (EMCR, PCI_Config, 0x00, 0x100) |
| 29 | Field (EMCR, DWordAcc, NoLock, Preserve) |
| 30 | { |
| 31 | Offset (0x84), /* PMECTRLSTATUS */ |
| 32 | D0D3, 2, /* POWERSTATE */ |
| 33 | Offset (0xa2), /* PG_CONFIG */ |
| 34 | , 2, |
| 35 | PGEN, 1, /* PG_ENABLE */ |
| 36 | } |
| 37 | |
| 38 | Method (_PS0, 0, Serialized) |
| 39 | { |
| 40 | /* Disable Power Good */ |
| 41 | Store (0, ^PGEN) |
| 42 | |
| 43 | /* Clear bits 31, 6, 2, 0 */ |
| 44 | ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA) |
| 45 | Sleep (2) |
| 46 | |
| 47 | /* Set bits 31, 6, 2, 0 */ |
| 48 | ^^PCRO (PID_SCS, 0x600, 0x80000045) |
| 49 | |
| 50 | /* Set Power State to D0 */ |
| 51 | Store (0, ^D0D3) |
| 52 | Store (^D0D3, Local0) |
| 53 | } |
| 54 | |
| 55 | Method (_PS3, 0, Serialized) |
| 56 | { |
| 57 | /* Enable Power Good */ |
| 58 | Store (1, ^PGEN) |
| 59 | |
| 60 | /* Set Power State to D0 */ |
| 61 | Store (3, ^D0D3) |
| 62 | Store (^D0D3, Local0) |
| 63 | } |
| 64 | |
| 65 | Device (CARD) |
| 66 | { |
| 67 | Name (_ADR, 0x00000008) |
| 68 | Method (_RMV, 0, NotSerialized) |
| 69 | { |
| 70 | Return (0) |
| 71 | } |
| 72 | } |
| 73 | } |
| 74 | |
| 75 | Device (SDXC) |
| 76 | { |
| 77 | Name (_ADR, 0x001E0006) |
| 78 | Name (_DDN, "SD Controller") |
| 79 | |
| 80 | OperationRegion (SDCR, PCI_Config, 0x00, 0x100) |
| 81 | Field (SDCR, DWordAcc, NoLock, Preserve) |
| 82 | { |
| 83 | Offset (0x84), /* PMECTRLSTATUS */ |
| 84 | D0D3, 2, /* POWERSTATE */ |
| 85 | Offset (0xa2), /* PG_CONFIG */ |
| 86 | , 2, |
| 87 | PGEN, 1, /* PG_ENABLE */ |
| 88 | } |
| 89 | |
| 90 | Method (_PS0, 0, Serialized) |
| 91 | { |
| 92 | /* Disable Power Good */ |
| 93 | Store (0, ^PGEN) |
| 94 | |
| 95 | /* Clear bits 8, 7, 2, 0 */ |
| 96 | ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A) |
| 97 | Sleep (2) |
| 98 | |
| 99 | /* Set bits 31, 6, 2, 0 */ |
| 100 | ^^PCRO (PID_SCS, 0x600, 0x00000185) |
| 101 | |
| 102 | /* Set Power State to D0 */ |
| 103 | Store (0, ^D0D3) |
| 104 | Store (^D0D3, Local0) |
| 105 | } |
| 106 | |
| 107 | Method (_PS3, 0, Serialized) |
| 108 | { |
| 109 | /* Enable Power Good */ |
| 110 | Store (1, ^PGEN) |
| 111 | |
| 112 | /* Set Power State to D0 */ |
| 113 | Store (3, ^D0D3) |
| 114 | Store (^D0D3, Local0) |
| 115 | } |
| 116 | |
| 117 | Device (CARD) |
| 118 | { |
| 119 | Name (_ADR, 0x00000008) |
| 120 | Method (_RMV, 0, NotSerialized) |
| 121 | { |
| 122 | Return (1) |
| 123 | } |
| 124 | } |
| 125 | } |