skylake: ACPI: Fix compiler warnings with iasl-20150717
Updating to a new IASL introduces a lot of warnings that are
not serious issues but can be fixed with some reworks.
- Method local variables that are set but never used now warn,
when needing to read back a register the ordering is now changed
to set the value in Local0 first so the compiler does not complain.
- Methods that create an object must be serialized
- A ResourceTemplate declared inside a _CRS with a named variable
does not seem to be able to compile without a warning. To fix
this move the ResourceTemplate outside the _CRS method.
- The DPTF CPU code was still using the old legacy \_PR.CPUx
instead of the new \_PR.CPxx definitions.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build glados with iasl-20150717 and see no warnings
Original-Change-Id: I4a66c7eb6495aac4ae1aa42100c846725c1a04d2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302168
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia3af802ca2faab4f1c59e73f2ce31a65c7e862e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11812
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
index 4eb9683..0a6d94b 100644
--- a/src/soc/intel/skylake/acpi/scs.asl
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -37,7 +37,7 @@
Method (_PS0, 0, Serialized)
{
- /* Disable Power Good */
+ /* Disable Power Gate */
Store (0, ^PGEN)
/* Clear bits 31, 6, 2, 0 */
@@ -48,17 +48,19 @@
^^PCRO (PID_SCS, 0x600, 0x80000045)
/* Set Power State to D0 */
- Store (0, ^D0D3)
+ Store (Zero, Local0)
+ Store (Local0, ^D0D3)
Store (^D0D3, Local0)
}
Method (_PS3, 0, Serialized)
{
- /* Enable Power Good */
+ /* Enable Power Gate */
Store (1, ^PGEN)
/* Set Power State to D0 */
- Store (3, ^D0D3)
+ Store (3, Local0)
+ Store (Local0, ^D0D3)
Store (^D0D3, Local0)
}
@@ -89,7 +91,7 @@
Method (_PS0, 0, Serialized)
{
- /* Disable Power Good */
+ /* Disable Power Gate */
Store (0, ^PGEN)
/* Clear bits 8, 7, 2, 0 */
@@ -100,17 +102,19 @@
^^PCRO (PID_SCS, 0x600, 0x00000185)
/* Set Power State to D0 */
- Store (0, ^D0D3)
+ Store (Zero, Local0)
+ Store (Local0, ^D0D3)
Store (^D0D3, Local0)
}
Method (_PS3, 0, Serialized)
{
- /* Enable Power Good */
+ /* Enable Power Gate */
Store (1, ^PGEN)
/* Set Power State to D0 */
- Store (3, ^D0D3)
+ Store (3, Local0)
+ Store (Local0, ^D0D3)
Store (^D0D3, Local0)
}