Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 3 | #include <cpu/x86/msr.h> |
| 4 | #include <cpu/x86/tsc.h> |
| 5 | #include <soc/msr.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 6 | |
Subrata Banik | 45a221d | 2015-08-05 17:01:55 +0530 | [diff] [blame] | 7 | static const unsigned int cpu_bus_clk_freq_table[] = { |
| 8 | 83333, |
| 9 | 100000, |
| 10 | 133333, |
| 11 | 116666, |
| 12 | 80000, |
| 13 | 93333, |
| 14 | 90000, |
| 15 | 88900, |
| 16 | 87500 |
| 17 | }; |
| 18 | |
| 19 | unsigned int cpu_bus_freq_khz(void) |
| 20 | { |
| 21 | msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 22 | |
| 23 | if ((clk_info.lo & 0xf) < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int))) |
| 24 | return cpu_bus_clk_freq_table[clk_info.lo & 0xf]; |
| 25 | |
Subrata Banik | 45a221d | 2015-08-05 17:01:55 +0530 | [diff] [blame] | 26 | return 0; |
| 27 | } |
| 28 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 29 | unsigned long tsc_freq_mhz(void) |
| 30 | { |
Subrata Banik | 45a221d | 2015-08-05 17:01:55 +0530 | [diff] [blame] | 31 | msr_t platform_info; |
| 32 | unsigned int bclk_khz = cpu_bus_freq_khz(); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 33 | |
Subrata Banik | 45a221d | 2015-08-05 17:01:55 +0530 | [diff] [blame] | 34 | if (!bclk_khz) |
| 35 | return 0; |
| 36 | |
| 37 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 38 | return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 39 | } |
| 40 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 41 | void set_max_freq(void) |
| 42 | { |
| 43 | msr_t perf_ctl; |
| 44 | msr_t msr; |
| 45 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 46 | /* Enable Intel SpeedStep */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 47 | msr = rdmsr(IA32_MISC_ENABLE); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 48 | msr.lo |= (1 << 16); |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 49 | wrmsr(IA32_MISC_ENABLE, msr); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 50 | |
Hannah Williams | b0eb594 | 2015-08-23 17:24:43 -0700 | [diff] [blame] | 51 | /* Enable Burst Mode */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 52 | msr = rdmsr(IA32_MISC_ENABLE); |
Hannah Williams | b0eb594 | 2015-08-23 17:24:43 -0700 | [diff] [blame] | 53 | msr.hi = 0; |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 54 | wrmsr(IA32_MISC_ENABLE, msr); |
Hannah Williams | b0eb594 | 2015-08-23 17:24:43 -0700 | [diff] [blame] | 55 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 56 | /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of the PERF_CTL */ |
Hannah Williams | b0eb594 | 2015-08-23 17:24:43 -0700 | [diff] [blame] | 57 | msr = rdmsr(MSR_IACORE_TURBO_RATIOS); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 58 | perf_ctl.lo = (msr.lo & 0x003f0000) >> 8; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 59 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 60 | /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of the PERF_CTL */ |
Hannah Williams | b0eb594 | 2015-08-23 17:24:43 -0700 | [diff] [blame] | 61 | msr = rdmsr(MSR_IACORE_TURBO_VIDS); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 62 | perf_ctl.lo |= (msr.lo & 0x007f0000) >> 16; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 63 | perf_ctl.hi = 0; |
| 64 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 65 | wrmsr(IA32_PERF_CTL, perf_ctl); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 66 | } |